Specifications

AN93
152 Rev. 0.9
a.Space U2, Q4, Q5, R1, R3, R4, R10 and R11
away from each other for best thermal
performance.
b.The tightest layout can be achieved by grouping
R6, C10, Q2, R3, R5, and Q1.
c.Place C3 next to D1.
d.Make the size of the Q3, Q4, and Q5 collector
pads each sufficiently large for the transistor to
safely dissipate 0.5 W under worst case
conditions. See the transistor data sheet for
thermal resistance and maximum operating
temperature information. Implement collector
pads on both the component and solder side, and
use vias between them to improve heat transfer
for best performance.
9. U2 pin 15 is also known as IGND. This is the ground
return path for many of the discrete components and
requires special mention:
a.Route traces associated with IGND using 20 mil
traces.
b.The area underneath U2 should be ground-filled
and connected to IGND (U2 pin 15). Ground fill
both the solder side and the component side and
stitch together using vias.
c.C5, C6, C7 IGND return path should be direct.
d.The IGND plane must not extend past Q4 and
Q5.
10.The traces from R7 to FB1 and from R8 to FB2
should be well matched. This can be achieved by
routing these traces next to each other as possible.
Ensure that these traces are not routed close to the
traces connected to C1 or C2.
11.Minimize all traces associated with Y1, C40, and
C41.
12.Decoupling capacitors (size 0.22 µF and 0.1 µF
capacitors connected to V
DA
, V
DB
, V
DD
) must be
placed next to those pins. Traces of these
decoupling capacitors back to the Si24xx GND pin
should be direct and short.
Figure 27. Reference Placement