Specifications

AN93
102 Rev. 0.9
The parallel interface uses the FIFOs to buffer data in
the same way as serial mode. The main difference is
the additional control pins, RD
, WR, CS, and the
addition of Parallel Interface Register 0 and Parallel
Interface Register 1. Flow control must be implemented
by monitoring TXE and RXF in Parallel Register 1.
There is no protection against FIFO overflow. Data
transmitted when the TX FIFO is full is lost.
The register, Parallel Interface register 0 or 1, available
to the Si2493/57/34/15/04 data pins, depends upon the
state of address pin A0. When A0 is low (logic 0), the
data pins D7–D0 and the parallel mode control pins
provide an interface to the transmit and receive FIFOs
through Parallel Interface Register 0. The functions of
D7–0 when A0 = 0
b
are listed in Table 72. When A0 is
high (logic 1), the data pins, D7–D0, and the parallel
mode control pins provide an interface to the signals in
Parallel Interface Register 1. The functions of D7–D0
when A0 = 1
b
are listed in Table 73. The maximum burst
data rate is approximately 350 kbps (45 kBps).
3.4.5. Parallel Interface Register 0
This register receives transmit data from the parallel
port and provides received data to the parallel port. In
parallel mode, eight data bits are loaded into the TX
FIFO for every parallel write to Register 0. Transmit and
receive flow control in the parallel mode is controlled by
the RTS
and CTS bits and the RXF and TXE bits in
Parallel Register 1. The operation of RTS
and CTS is
analogous to that in Serial mode. These bits control the
transfer of data to and from a 1024 byte software buffer.
Flow control with TXE prevents block writes from
overflowing the TX hardware FIFO. All bits in this
register are read/write. The register resets to 0x63 after
a manual or power-on reset.
3.4.6. Parallel Interface Register 1
This register controls the flow of data in the parallel
mode and is reset to 0x63.
Bit 7 (RXF) is a read/write bit that gives the status of the
12-byte deep receive FIFO. If RXF = 0
b
, the receive
FIFO contains less than 10 bytes. If RXF = 1
b
, the
receive FIFO contains more than 9 bytes and is full or
almost full. Writing RXF = 0
b
clears the interrupt.
Bit 6 (TXE) is a read/write bit that gives the status of the
14-byte deep transmit FIFO. If TXE = 0
b
, the transmit
FIFO contains three or more bytes. If TXE = 1
b
, the
transmit FIFO contains two or fewer bytes. Writing
TXE = 0
b
clears the interrupt but does not change the
state of TXE.
Bit 5 (REM) is a read-only bit that indicates when the
receive FIFO is empty. If REM = 0
b
, the receive FIFO
contains valid data. If REM = 1
b
, the receive FIFO is
empty. The timer interrupt set by U6F ensures that RX
FIFO contents ≤ 9 bytes are serviced properly.
Bit 4 (INTM) is a read/write bit that controls whether or
not INT (bit 3) triggers the INT
pin (Si2493/57/34/15/04,
pin 15 in the parallel mode).
Bit 3 (INT) is a read-only bit that reports Interrupt status
in the parallel mode. If INT = 0
b
, no interrupt has
occurred. If INT = 1
b
, an interrupt due to CID, OCD,
PPD, RI, or DCD (U70 bits 4, 3, 2, 1, 0, respectively)
has occurred. This bit is reset by :I.
Table 71. Pin Function Changes in Parallel
Interface Mode
Pin Serial Mode
Function
Parallel Mode
Function
3CLKOUT A0
8RTS
D7
9RXD RD
10 TXD WR
11 CTS CS
15 AOUT INT
16 INT D0
17 RI
D1
22 ESC D3
23 DCD
D4
Table 72. Parallel Interface Register 0 Bit Map
Bit Name Function
7:0 TX/RX[7:0] Transmit/Receive Data
Table 73. Parallel Register 1 Signals
Data Bit Signal Function
D7 RXF Receive FIFO Almost Full
D6 TXE Transmit FIFO Almost Full
D5 REM Receive FIFO Empty
D4 INTM Interrupt Mask
D3 INT Interrupt
D2 ESC Escape
D1 RTS
Request-to-Send
D0 CTS
Clear-to-Send