Specifications

AN93
Rev. 0.8 95
.
Figure 19. UART Serial Interface
Parallel Interface
The parallel interface is intended for applications where
a serial interface is not available. The parallel interface
has an 8-bit data bus and a single address bit. The
parallel interface is selected by forcing AOUT/INT
(Si2493/57/34/15/04 Pin 15) to a logic 0 (low) through
an external pulldown resistor ≤ 10 kΩ. 27 MHz
operation is possible in the parallel mode. See Table 26
on page 53 for details. Several pins on the Si2457
change function when the parallel interface mode is
selected. Refer to “AN60: Si2493/57/34/15/04 Parallel
Interface Software” for detailed parallel interface
applications information (see note below).
Table 71 shows the function of the affected pins in the
serial and parallel interface modes.
Note: The parallel port has been modified in Si2456 revision
H and Si2457 revision B and later to allow interrupt
driven operation and remove the requirement of using
CTS and RTS for flow control (see “AN60: Si2456/33/
14 Parallel Interface Software”). Updates that may
affect existing host software written for the Si2456 fam-
ily with revisions before revision H or the Si2457 family
revision A are:
1. It is possible to clear the RXF bit by writing '0' in this
bit position of parallel register 1. It is recommended
that this bit always be written with '1' unless intention-
ally clearing the RXF bit to remove an RXF interrupt.
2. An inactivity timer controlled by register U6F will
assert an interrupt if data is available in the RX FIFO
for U6F milliseconds (default 255).
This is important to note when upgrading a hardware
design from the Si2456 family to the Si2457 family. A
small change to existing host software may be neces-
sary.
11 Bits
to Data Bus
CONTROL
RX Shift
Register
TX Shift
Register
TX FIFO
MUX
TXD
(10)
CTS
(11)
RTS
(8)
RXD
(9)
INT
(16)
RX FIFO