Specifications

AN93
Rev. 0.8 9
Power Supply and Bias Circuitry (Si2493/
57/34/15/04)
Power supply bypassing is important for the proper
operation of the Si2493/57/34/15/04, the suppression of
unwanted radiation and prevention of interfering signals
and noise from being coupled into the modem via the
power supply. C50 and C52 provide filtering of the 3.3 V
system power and must be located as close to the
Si2493/57/34/15/04 chip as possible to minimize lead
lengths. The best practice is to use surface mount
components connected between a power plane and a
ground plane. This technique minimizes the inductive
effects of component leads and PCB traces and
provides bypassing over the widest possible frequency
range.
Two bias voltages used inside the modem chip require
external bypassing and/or clamping. VDA (pin 7) is
bypassed by C51. VDB (pin19) is bypassed by C53.
R12 and R13 are optional resistors that can, in some
cases, reduce radiated emissions due to signals
associated with the isolation capacitor. These
components must be located as close to the Si2493/57/
34/15/04 chip as possible to minimize lead lengths. The
best practice is to use surface mount components
connected to a ground plane. This technique minimizes
the inductive effects of component leads and PCB
traces, provide bypassing over the widest possible
frequency range, and minimize loop areas that can
radiate radio-frequency energy.
Isolation Capacitor Interface
The ISOcap is a proprietary high-speed interface
connecting the modem chip and the DAA chip through a
high-voltage isolation barrier provided by capacitors C1
and C2. The ISOcap serves three purposes. First, it
transfers control signals and transmit data from the
modem chip to the DAA chip. Secondly, it transfers
receive and status data from the DAA chip to the
modem chip. Finally, it provides power from the modem
chip to the DAA chip while the modem is in the on-hook
condition. The signaling on this interface is intended for
communication between the modem and the DAA chips
and cannot be used for any other purpose. It is
important to keep the length of the ISOcap path as short
and direct as possible. The layout guidelines for the pins
and components associated with this interface are
described in "Appendix A—ISOmodem® Layout
Guidelines" on page 154 and must be carefully followed
to ensure proper operation and avoid unwanted
emissions.
System Interface
There are two system interface options, serial and
parallel. The serial interface allows the host processor
to communicate with the modem controller through a
UART driver. In this mode, the modem is analogous to
an external “box” modem. The interface pins are 5 V
tolerant, and communicate with TTL compatible low-
voltage CMOS levels. RS232 interface chips, such as
those used on the Si2457/34/15URT-EVB evaluation
board, can be used to make the serial interface directly
compatible with a PC or terminal serial port. The
operation of these pins is described in the section,
"Software Design Reference" on page 18.
DAA (Line-Side) Device
The Si3018/10, DAA or line-side device, contains an
ADC, a DAC, control circuitry, and an ISOcap™
interface. The Si3018/10 and surrounding circuitry
provide all functionality for telephone line interface
requirement compliance including a full-wave bridge,
hookswitch, dc termination, ac termination, ring detect,
loop voltage/current monitoring, and call progress
monitoring. A schematic of the Si3018/10 circuitry is
shown in Figure 2 with the component functions
identified. Additionally, the Si3018/10 external circuitry
is largely responsible for EMI, EMC, safety, and surge
performance.
Power Supply and Bias Circuitry
(Si3018/10)
The Si3018/10 is powered by a small current passed
across the ISOcap™ in the on-hook mode and by the
loop current in the off-hook mode. Since there is no
system ground reference for the line-side chip due to
isolation requirements, a virtual ground, IGND, is used
as a reference point for the Si3018/10. Several bias
voltages and signal reference points used inside the
DAA chip require external bypassing, filtering, and/or
clamping. VREG2 (pin 10) is bypassed by C6. VREG
(pin 7) is bypassed by C5. These components must be
located as close to the Si3018/10 chip as possible to
minimize lead lengths. The best practice is to use
surface mount components and very short PCB trace
lengths to minimize the inductive effects of component
leads and PCB traces thereby bypassing over the
widest possible frequency range and minimizing loop
areas that can radiate radio-frequency energy.