Specifications

AN93
84 Rev. 0.8
U70 (IO0)
U70 controls escape and several indicator and detector
masks and provides several read-only status bits. (See
Table 60.) Bits 5, 6, 7, and 14 are reserved.
Bits 4:0 are read only, and bits 15 and 13:8 are read/
write. U70 resets to 0x2700 with a power-on or manual
reset.
Bit 15 (HES) = 0
b
(default) disables the hardware
escape pin (Si2493/57/34/15/04, pin 22 [ESC]). Setting
HES = 1
b
enables ESC. When ESC is enabled, escape
from the data mode to the command mode occurs at the
rising edge of the ESC pin. Multiple escape options can
be enabled simultaneously. For example, U70[13] (TES)
=1
b
by default, which enables the “+++” escape. If HES
is also set (HES = 1
b
), either escape method works.
Additionally, the 9th bit escape can also be enabled with
the AT\B6 command or through autobaud.
Bit 13 (TES) = 1
b
(default) enables the traditional “+++”
escape sequence. To successfully escape from data
mode to command mode using “+++”, there must be no
UART activity for a guard period, determined by register
S12, both before and after the “+++”. S12 can be set for
a period ranging from 200 ms to 5.1 seconds.
Bit 12 (CIDM) = 0
b
(default) prevents a change in
U70[4] (CID), caller ID, from triggering an interrupt. If
CIDM = 1
b
, an interrupt is triggered with a low-to-high
transition on CID.
Bit 11 (OCDM) = 0
b
(default), an interrupt is not
triggered with a change in OCD. If OCDM = 1
b
a low-to-
high transition on U70[3] (OCD), overcurrent detect,
triggers an interrupt. This bit must be set for Australia
and Brazil.
Bit 10 (PPDM) = 1
b
(default) causes a low-to-high
transition in U70[2] (PPD), parallel phone detect, to
trigger an interrupt. If PPDM = 0
b
, an interrupt is not
triggered with a change in PPD.
Bit 9 (RIM) = 1
b
(default) causes a low-to-high transition
in U70[1] (RI), ring indicator, to trigger an interrupt. If
RIM = 0
b
, an interrupt is not triggered with a change in
RI.
Bit 8 (DCDM) = 1
b
(default) causes a high-to-low
transition in U70[0] (DCD), data carrier detect, to trigger
an interrupt. If DCDM = 0
b
, an interrupt is not triggered
with a change in DCD.
Bits 4:0 are the event indicators described below. All are
“sticky” (i.e., remain set to 1
b
after the event) and clear
on an interrupt read (AT:I).
Table 60. U70 Bit Map
Bit Name Function
15 HES Enable Hardware Escape Pin.
0 = Disable.
1 = Enable.
14 Reserved Read returns zero.
13 TES Enable Escape (+++).
0=Disable.
1 = Enable.
12 CIDM Caller ID Mask.
0 = Change in CID does not affect INT
.
1 = CID low-to-high transition triggers INT
.
11 OCDM Overcurrent Detect Mask.
0 = Change in OCD does not affect INT.
(“X” result code is not generated in command mode.)
1 = OCD low-to-high transition triggers INT.
(“X” result code is generated in command mode.)
10 PPDM Parallel Phone Detect Mask.
0 = Change in PPD does not affect INT
.
1 = PPD low-to-high transition triggers INT
.