Specifications

AN93
56 Rev. 0.8
Figure 14. EEPROM Serial I/O Timing
Table 29. EEPROM Timing
Parameter Symbol Min. Typ. Max. Unit
EECLK period ECLK 1.0 — — µs
EESD input setup time EISU 100 — — ns
EESD input hold time EIH 100 — — ns
EESD output setup time* EOSU 500 — — ns
EESD output hold time* EOH 500 — — ns
EECS
asserted to EECLK positive edge ECSS 500 — — ns
EESD tristated before last falling EECLK edge during read
cycle. Last positive half of EECLK cycle is extended to pro-
vide both 500 ns minimum EOH and 100 ns EESD before
EECLK falling edge.
EOZ 100 — — ns
EECS
disable time between accesses ECSW 500 — — ns
EECS
asserted after final EECLK edge ECSH 1 — — µs
*Note: EESD output at negative EECLK edge
ECLK
LSB
MSB
EISU
EOSU
EIH
EDH
ECSH
ECSW
EOZ
ECSS
EEPROM Data Format
EESD
EECS
8-bit instruction 16-bit address 8-bit data
EOH