Specifications

AN93

Rev. 0.8 55

AT25080—AT25640 Atmel

The EEPROM must be between 8192 and 65536 bits in

size and support the commands given in Table 28. The

EEPROM must also support 16-bit addressing

regardless of size, allow a minimum clock frequency of

1 MHz, and should assert its output on falling edges of

EECLK and latch input data on rising edges of EECLK.

A four-wire EEPROM (with separate serial input and

output data wires may be used with the input and output

pins connected to EESD so long as SDO is tristated on

the last falling edge of EECLK during a read cycle. All

data is sent to and from the EEPROM with the LSB first.

Figure 13 shows the connection diagram for the

EEPROM feature.

Figure 13. EEPROM Connection Diagram

WEL = write enable latch

WIP = write in progress

SPI

EEPROM

HOST

Si2457/34/15/04

TELEPHONE

LINE

SO/SI

EECS

SCLK

EESD

EECLK

Si3018/10

Table 27. EEPROM Status Register (Any Other Bits are Unused)

76543210

––––––WELWIP

Table 28. EEPROM Commands

Instruction Name Instruction Format Description

READ 0000 0011 Read data from memory at address

WRITE 0000 0010 Write data to memory array beginning at address

WRDI 0000 0100 Clear write enable bit (disable write operation)

RDSR 0000 0101 Read status register

WRSR 0000 0001 Write status register

WREN 0000 0110 Set write enable bit (enable write operations)