Specifications

AN93
52 Rev. 0.8
Figure 12. “9th Bit” Escape Timing
Sleep Mode
The Si2493/57/34/15/04 can be set to enter a low power
sleep mode when not connected and after a period of
inactivity determined by the S24 register. The Si2493/
57/34/15/04 enters the sleep mode S24 seconds after
the last DTE activity, the TX FIFO is empty, and the last
data is received from the remote modem. The Si2493/
57/34/15/04 returns to the active mode when there is a
1 to 0 transition on TXD in the serial mode or a 1 to 0
transition on CS
in the parallel mode or if an incoming
ring is detected. The delay range for S24 is 1 to 255
seconds. The default setting of S24 = 0 disables the
sleep timer and keeps the modem in the normal power
mode regardless of activity level.
Powerdown
The powerdown mode is a lower power state than sleep
mode but is entered immediately upon writing
U65[13] (PDN) = 1. Once in the powerdown mode, the
modem requires a hardware reset via the RESET
pin
(Si2493/57/34/15/04, pin 12) to become active.
Reset/Default Settings
The modem must be reset after power is stable and
prior to the first “AT” command. The reset pin (Si2493/
57/34/15/04, pin 12) must be asserted at least 5 ms low
to adequately reset the on-chip registers.
CTS
(pin 11) must remain at a Logic 1 (high state)
during Reset. The internal pull-up resistor is adequate
for most applications. If leakage or transients are
present on CTS
during Reset, the high value internal
resistor should be supplemented with an external 10 kΩ
resistor to V
CC
.
Autobaud is enabled on the DTE by default. A 10 kΩ
resistor connected from EESD/D2 (Si2493/57/34/15/04
pin 18) to GND (Si2493/57/34/15/04 pin 20) disables
autobaud on powerup or reset and forces 19.2 kbps.
Serial or parallel interface selection depends upon the
state of Si2493/57/34/15/04, pin 15, AOUT/INT
, at the
rising edge of the reset pulse. If AOUT/INT
is left open,
an internal pullup resistor holds the pin at a logic 1, and
the serial interface is selected (default). If AOUT/INT
is
connected to ground through a 10 kΩ resistor, the
parallel interface is selected.
A 10 kΩ resistor between D6 (Si2493/57/34/15/04 pin 4)
and GND (Si2493/57/34/15/04 pin 20) enables the
EEPROM interface on powerup or reset. Table 26
summarizes the options for enabling features on
powerup and reset by connecting a 10 kΩ resistor
between the indicated Si2493/57/34/15/04 pin and GND
(Si2493/57/34/15/04 Pin20). Zeroes indicate a <10 k
pulldown to ground at startup or reset; “1”s indicate
internal pullup (do not pull down externally), and “X”s
indicate a don’t care.
UART Timing for Modem Transmit Path (9N1 Mode with 9th Bit Escape)
D0 D1 D2 D3 D4 D5 D6 ESCD7 StopStart
CTS
TX
t
RTS
t
CTH
9-Bit Data
Mode