Specifications

AN93
Rev. 0.8 21
The synchronous access mode has additional features
compared against the Legacy Synchronous DCE Mode.
For new designs, use the newer synchronous access
mode interface. Otherwise, if there is existing software
written with the Legacy Synchronous DCE Mode
interface, no software changes are required as long as
the AT+ES command settings are not changed from the
default value.
Legacy Synchronous DCE Mode
As shown in Table 10, this Legacy Synchronous DCE
Mode is chosen as long as the AT+ES setting is set to
its default value of +ES = D,,D.
The fast connect transparent HDLC modes are enabled
via U7A and require wire mode operation (\N0). Each of
the stages (answer tone detect time, unscrambled ones
detect time, etc.) in the connect sequence may be
shortened. The amount that each of these are
shortened when in fast connect mode depends on the
modulation. (See Table 11.) The "transparent HDLC"
mode of operation operates with an asynchronous DTE
and a synchronous DCE. The Si2493/57/34/15/04
performs HDLC frame packing and unpacking, frame
opening and closing, flag generation and detection,
CRC computation and checking, and 0 insertion and
deletion. To use this mode, the DTE rate must be
greater than the DCE rate; flow control via either CTS
or
/Q and /S must be used and wire mode operation (\N0)
is required. (See Table 12.)
On the transmit side, if no data is received on TXD, the
Si2493/57/34/15/04 continually transmits HDLC flags at
the DCE. As soon as there are 10 characters sent into
the transmit buffer, the Si2493/57/34/15/04 begins an
HDLC frame at the DCE. The reason for this 10-
character “head start” is to reduce the likelihood of an
underrun once the HDLC frame has begun at the DCE.
As long as the host continues to send data, the Si2493/
57/34/15/04 continues to zero insert, update the CRC
value, and send data within an HDLC frame. To properly
end the frame, the host must send a /Zn (see Table 12)
indicating to the Si2493/57/34/15/04 the end of the
frame. Once the Si2493/57/34/15/04 encounters the /
Zn, it computes and sends the final CRC and begins
transmitting HDLC flags.
If an HDLC frame is smaller than the 10-character “head
start”, the HDLC frame is started at the DCE upon
receipt of the /Zn character. The /Tn metacharacter is
sent to the host to provide an indication that an HDLC
frame was sent successfully.
Table 10. Synchronous Mode Overview
Synchronous Mode U-Register AT+ES Settings
Neither U7A[2] = 0 +ES = D,,D
Legacy Synchro-
nous DCE Mode
U7A[2] = 1 +ES = D,,D
Synchronous Access
Mode
+ES = 6,,8
Table 11. Fast Connect/Legacy Synchronous
DCE
Protocol DCE Register
Settings
All Normal, Asynchro-
nous
&Hn, \N0,
AT+ES = D,,D
V.22,
Bell212,
V.22bis
Normal, Transparent
HDLC
&H6, 7, 8, \N0
U7A = 0002,
AT+ES = D,,D
Bell103, V.21 Fast connect,
Asynchronous
&H9, 10, \N0
U7A = 0001,
AT+ES = D,,D
V.22, Bell212 Fast connect,
Asynchronous
&H7, \N0
U7A = 0001,
AT+ES = D,,D
V.22, Bell212 Fast connect,
Transparent HDLC
&H7, \N0
U7A = 0003,
AT+ES = D,,D
V.22bis Transparent HDLC &H6, \N0
U7A = 0002,
AT+ES = D,,D