Specifications

AN93
154 Rev. 0.8
APPENDIX A—ISOMODEM
®
LAYOUT GUIDELINES
Layout Guidelines
The key to a good layout is proper placement of
components. It is best to copy the placement shown in
Figure 27. Alternatively, perform the following steps,
referring to the schematics and Figure 28. It is strongly
recommended to complete the checklist in Table 101
while reviewing the final layout.
1. All traces, open pad sites and vias connected to the
following components are considered to be in the DAA
section, and must be physically separated from non-DAA
circuits by 5 mm to achieve best possible surge
performance: R1, R2, R3, R4, R5, R6, R6, R8, R9, R10,
R11, R15, R16, U2, Z1, D1, FB1, FB2, RJ11, Q1, Q2, Q3,
Q4, Q5, C3, C4, C5, C6, C7, C8, C9, C10, RV1, C1 pin 2
only, C2 pin 2 only, C8 pin 2 only, C9 pin 2 only.
2. The Isolation Capacitors C1, C2, C8 and C9 are the only
components permitted to straddle between the DAA
section and non-DAA section components and traces. This
means that for each of these capacitors, one of the
terminals is on the DAA-side, the other is not. Maximize
the spacing between the terminals (between pin 1 to pin 2)
of each of these capacitors.
3. Place and group the following components: U1, U2, R12,
R13, C1, C2.
a.U1 and U2 are placed so that the right side of U1 faces
the left side of U2.
b.C1 and C2 should be placed directly between U1 and
U2.
c.Keep R12 and R13 close to U1.
d.Place U1, U2, C1, and C2 so that the recommended
minimum creepage spacing for the target application is
implemented.
e.Place C1 and C2 so that traces connected to U2 pin 5
(C1B) and U2 pin 6 (C2B) are physically separated
from traces connected to:
i.C8, R15, FB1
ii.C9, R16, FB2
iii.U2 pin 8, R7
iv.U2 pin 9, R9
4. Place and group the following components around U2: C4,
R9, C7, R2, C5, C6, R7, R8. These components should
form the critical 'inner circle' of components around U2.
a.Place C4 close to U2 pin 3. This is best achieved by
placing C4 northwest of U2.
b.Place R9 close to U2 pin 4. This is best achieved by
placing R9 horizontally, directly to the north of U2.
c.Place C7 close to U2 pin 15. This is best achieved by
placing C7 next to R9.
d.Place R2 next to U2 pin 16. This is best achieved by
placing R2 northeast of U2.
e.Place C6 close to U2 pin 10. This is best achieved by
placing C6 southeast of U2.
f.Place R7 and R8 close to U2. This is best achieved by
placing these components to the south of U2.
g.Place C5 close to U2 pin 7. This is best achieved by
placing C5 southwest of U2.
5. Place Q5 next to R2 so that the base of Q5 can be
connected to R2 directly.
6. Place Q4 such that the base of Q4 can be routed to U2 pin
13 easily, and that the emitter of Q4 can be routed to U2
pin 12 easily. Route these two traces next to each other so
that the loop area formed by these two traces are
minimized.
7. Place and group the following components around the
RJ11 jack: FB1, FB2, RV1, R15, R16, C8 and C9.
a.Use 20 mil width traces on this grouping to minimize
impedance.
b.Place C8 and C9 close to the RJ11 jack, recognizing
that, a GND trace will be routed between C8 and C9,
back the Si24xx GND pin, through a 20-mil width trace.
The GND trace from C8 and C9 must be isolated from
the rest of the Si3018/10 traces.
c.The trace from C8 to GND and the trace from C9 to
GND must be short and equidistant.
8. After the previous step, there should be some space
between the grouping around U2 and the grouping of
components around the RJ11 jack. Place the rest of the
components in this area, given the following guidelines:
a.Space U2, Q4, Q5, R1, R3, R4, R10 and R11 away
from each other for best thermal performance.
b.The tightest layout can be achieved by grouping R6,
C10, Q2, R3, R5 and Q1.
c.Place C3 next to D1.
d.Make the size of the Q4 and Q5 collector pad larger to
improve heat dissipation. Implement collector pads on
solder side and use vias between them to improve heat
transfer.
9. U2 pin 15 is also known as IGND. This is the ground return
path for many of the discrete components, and requires
special mention
a.Route traces associated with IGND using 20 mil
traces.
b.The area underneath U2 should be ground-filled and
connected to IGND (U2 pin 15). Ground fill both solder
side and component side and stitch together using
vias.