Specifications

Si2457/34/15/04
6 Rev. 1.3
Table 4. AC Characteristics
(V
D
= 3.0 to 3.6 V, TA = 0 to 70 °C for F-grade, Fs = 8 kHz, T
A
= –40 to 85 °C for G-grade)
Parameter Symbol Test Condition Min Typ Max Unit
Sample Rate Fs — 8 — kHz
Clock Input Frequency F
XTL
default — 4.9152 — MHz
Clock Input Frequency F
XTL
27 MHz Mode
1
—27—MHz
Clock Input Frequency F
XTL
32 kHz Mode
1
— 32.768 — kHz
Receive Frequency Response Low –3 dBFS Corner, FILT = 0 — 5 — Hz
Receive Frequency Response Low –3 dBFS Corner, FILT = 1 — 200 — Hz
Transmit Full Scale Level
2
V
FS
—1.1—V
PEAK
Receive Full Scale Level
2,3
V
FS
—1.1—V
PEAK
Dynamic Range
4
DR ILIM = 0, DCV = 11, MINI = 00
DCR = 0, I
L
= 100 mA
—80— dB
Dynamic Range
4
DR ILIM = 0, DCV = 00, MINI = 11
DCR = 0, I
L
=20mA
—80— dB
Dynamic Range
4
DR ILIM = 1, DCV = 11, MINI = 00
DCR = 0, I
L
=50mA
—80— dB
Transmit Total Harmonic
Distortion
5
THD ILIM = 0, DCV = 11, MINI = 00
DCR = 0, I
L
= 100 mA
—–72— dB
Transmit Total Harmonic
Distortion
5
THD ILIM = 0, DCV = 00, MINI = 11
DCR = 0, I
L
=20mA
—–78— dB
Receive Total Harmonic
Distortion
5
THD ILIM = 0, DCV = 00, MINI = 11
DCR = 0, I
L
=20mA
—–78— dB
Receive Total Harmonic
Distortion
5
THD ILIM = 1,DCV = 11, MINI=00
DCR = 0, I
L
=50mA
—–78— dB
Dynamic Range (Caller ID Mode) DR
CID
VIN = 1 kHz, –13 dBm — 50 — dB
Notes:
1. Refer to “AN93: ISOmodem
®
Chipset Family Designer's Guide” for configuring clock input reset strapping.
2. Measured at TIP and RING with 600 termination at 1 kHz, as shown in Figure 1 on page 5.
3. Receive full scale level produces –0.9 dBFS at DTX.
4. DR = 20 x log |Vin| + 20 x log (rms signal/rms noise). Applies to both transmit and receive paths. Vin = 1 kHz, –3 dBFS.
5. Vin = 1 kHz, –3 dBFS. THD = 20 x log (rms distortion/rms signal).