Si2404
Rev. 0.91 9
Figure 3. Parallel Interface Read Timing
Figure 4. Parallel Interface Write Timing
t
CSH
t
CSS
t
AS
t
AH
ADDRESS = 0 or 1
t
RL
t
RC
t
RLDD
t
DH
t
RLDD
VALID DATA VALID DATA
A0
D[7:0]
CS
RD
t
DZ
t
CSH
t
CSS
t
AS
t
AH
t
WC
t
WL
ADDRESS = 0 or 1
t
WDSU
t
DH
VALID DATA VALID DATA
A0
D[7:0]
CS
WR
