User Guide

C8051T620/2-DK
Rev. 0.4 9
Figure 3. C8051T62x Motherboard
Figure 4. C8051T62x Motherboard Default Shorting Block Positions
P3
SILICON LABS
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RESET
J15
J7
USB ACTIVE
J5
J14
SW1
J12
J13
J1
DEBUG
PWR
RUN
VDD_PWR
VDD_PWR
VDD_PWR
VDD_PWR
+3VD
VDD_EXT
VDD_DEBUG
VDD_COMM
J6
P2
P1
J2
SW2
J3
J4
USB ACTIVE
LED1
PWR
D10
D11 D12
R8
U2
CP2103
U1
F326
STOP
LED1
J10
P2.2
P0.6
LED2
P2.3
P1.2
SW1
J9
P2.0
P0.1
SW2
P2.1
P1.0
C8051T62x-MB
LED2
VPP
P5
P4
J8
CTS_DEBUG
P1.1 P1.2
RTS_COMM CTS_COMM
RTS_DEBUG
J11
TX_DEBUG
P0.4 P0.5
RX_COMM TX_COMM
RX_DEBUG
P3
SILICON LABS
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RESET
J15
J7
USB ACTIVE
J5
J14
SW1
J12
J13
J1
DEBUG
PWR
RUN
VDD_PWR
VDD_PWR
VDD_PWR
VDD_PWR
+3VD
VDD_EXT
VDD_DEBUG
VDD_COMM
J6
P2
P1
J2
SW2
J3
J4
USB ACTIVE
LED1
PWR
D10
D11 D12
R8
U2
CP2103
U1
F326
STOP
LED1
J10
P2.2
P0.6
LED2
P2.3
P1.2
SW1
J9
P2.0
P0.1
SW2
P2.1
P1.0
C8051T62x-MB
LED2
VPP
P5
P4
J8
CTS_DEBUG
P1.1 P1.2
RTS_COMM CTS_COMM
RTS_DEBUG
J11
TX_DEBUG
P0.4 P0.5
RX_COMM TX_COMM
RX_DEBUG