User's Manual

Silicon Laboratories Finland Oy
Page 22 of 45
6.1 UART Bypass
Figure 12: UART Bypass Architecture
6.2 UART Configuration While Reset is Active
The UART interface for WT41u while the chip is being held in reset is tristate. This will allow the user to daisy
chain devices onto the physical UART bus. The constraint on this method is that any devices connected to
this bus must tristate when WT41u reset is de-asserted and the firmware begins to run.
6.3 UART Bypass Mode
Alternatively, for devices that do not tristate the UART bus, the UART bypass mode on the chipset can be
used. The default state of the chipset after reset is de-asserted; this is for the host UART bus to be connected
to the chipset UART, thereby allowing communication to the chipset via the UART. All UART bypass mode
connections are implemented using CMOS technology and have signalling levels of 0V and VDD.
In order to apply the UART bypass mode, a BCCMD command will be issued to the chipset. Upon this issue, it
will switch the bypass to PIO[7:4] as Figure 11 indicates. Once the bypass mode has been invoked, WT41u
will enter the Deep Sleep state indefinitely.
In order to re-establish communication with WT41u, the chip must be reset so that the default configuration
takes effect.
It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass
mode is invoked. Therefore, it is not possible to have active Bluetooth links while operating the bypass mode.
The current consumption for a device in UART bypass mode is equal to the values quoted for a device in
standby mode.