User's Manual

PCM_OUT

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Sign extension

8-bit sample

Figure 30: 16-bit slot with 8-bit companded sample and sign extension selected

PCM_OUT

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8-bit sample

Zeros padding

Figure 31: 16-bit slot with 8-bit companded sample and zeros padding selected

PCM_OUT

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3-bit sign

extension

13-bit sample

Figure 32: 16-bit slot with 13-bit linear sample and sign extension selected

PCM_OUT

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Audio gain

13-bit sample

Figure 33: 16-bit slot with 13-bit linear sample and audio gain selected

7.4.7 Additional Features

WT32 has a mute facility that forces PCM_OUT to be 0. In Master mode, PCM_SYNC may also be

forced to 0 while keeping PCM_CLK running, which some CODECS use to control power down.

7.4.8 PCM CLK and SYNC Generation

WT32 has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is

generating these signals by Direct Digital Synthesis (DDS) from BlueCore5 Multimedia External internal

4MHz clock. Using this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz. The

second is generating PCM_CLK and PCM_SYNC by DDS from an internal 48MHz clock (which allows a

greater range of frequencies to be generated with low jitter, but consumes more power). The second

method is selected by setting bit 48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this

mode and with long frame sync, the length of PCM_SYNC can be either 8 or 16 cycles of PCM_CLK,

determined by LONG_LENGTH_SYNC_EN in PSKEY_PCM_CONFIG32.

Equation 3 describes PCM_CLK frequency when being generated using the internal 48MHz clock:

Equation 3: PCM_CLK frequency when being generated using the internal 48 MHz clock

The frequency of PCM_SYNC relative to PCM_CLK can be set using Equation 4

Equation 4: PCM_SYNC frequency relative to PCM_CLK

CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an

example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set

PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.