User's Manual
18
4 WT32 Pin Description
AUDIO_OUT_N_LEFT
AUDIO_OUT_P_LEFT
AUDIO_OUT_P_RIGHT
AUDIO_OUT_N_RIGHT
AGND
AUDIO_IN_N_LEFT
AUDIO_IN_P_LEFT
AGND
AUDIO_IN_N_RIGHT
AUDIO_IN_P_RIGHT
MIC_BIAS
AGND
VDD_CHG
VDD_BAT
LED0
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_NCSB
PCM_CLK
PCM_SYNC
PCM_OUT
PCM_IN
PIO4
PIO5
PIO6
PIO7
PIO8
UART_NCTS
UART_NRTS
RESET
DGND
VDD_IO
UART_TXD
UART_RXD
PIO10
PIO9
USB_D+
USB_D-
PIO3
PIO2
PIO1
PIO0
AIO1
AIO0
DGND
DGND
DGND
RF
1
17 31
50
RFTP
DGND
VREG_ENA
Figure 2: WT32 connection diagram (top view)
NOTE: VREG_ENA pin is only available with the production version of the module. With engineering
samples the VREG_ENA is internally connected to VDD_BAT.
DEVICE TERMINALS
1
VREG_ENA
2
DGND
3
DGND
4
DGND
5
AIO1
6
AIO0
7
PIO0
8
PIO1
9
PIO2
10
PIO3
11
USB_DN
12
USB_DP
13
PIO9
14
PIO10
15
RXD
16
TXD
17
VDD_IO
18
DGND
19
RESET