WT32 DATA SHEET Thursday, 12 September 2013 Version 2.
Copyright © 2000-2013 Bluegiga Technologies All rights reserved. Bluegiga Technologies assumes no responsibility for any errors which may appear in this manual. Furthermore, Bluegiga Technologies reserves the right to alter the hardware, software, and/or specifications detailed here at any time without notice and does not make any commitment to update the information contained here. Bluegiga’s products are not authorized for use as critical components in life support devices or systems.
VERSION HISTORY Version Comment 1.0 Soldering recommendations added. Layout guide VREG_ENA. Operating temperature range fixed. 1.1 Bluetooth and FCC qualification IDs added 1.2 Figure 18 fixed. Recommendation for external ESD protection removed. 1.3 Changed VREG_ANA to VREG_ENA 1.4 Radiocharacteristics updated 1.5 List of pretested antennas added 1.51 Table 1 corrected 1.52 PSKEY_PCM_CONFIG32 description corrected 1.53 Table 4: minor correction 1.6 Dimensions updated 1.
2.18 Added additional note about SPDIF 2.19 Minor changes 2.
TABLE OF CONTENTS 1 Ordering Information......................................................................................................................................9 2 Block Diagram and Descriptions ................................................................................................................ 10 3 Electrical Characteristics ............................................................................................................................ 12 3.
7.2.3 IEC 60958 Interface ..................................................................................................................... 39 7.2.4 Microphone Input ......................................................................................................................... 40 7.2.5 Line Input ..................................................................................................................................... 42 7.2.6 Output Stage .....................................
16 Contact Information.................................................................................................................................
WT32 Bluetooth® Audio Module DESCRIPTION: KEY FEATURES: WT32 is a Bluetooth 2.1 + EDR module dedicated for Bluetooth audio applications. In addition to Bluetooth radio, antenna and iWRAP Bluetooth stack, WT32 contains a DSP processor, a stereo audio codec and a battery charger making it ideal for portable battery Bluetooth stereo or hands-free audio applications.
1 Ordering Information WT32-A-AI Fimrware AI5 AI4 C = = = HW version A = E = iWRAP 5.0.0 iWRAP 4.0.0 *) custom Chip antenna, industrial temperature range W.FL connector, industrial temperature range Product series *) Custom firmware refers to any standard firmware with custom parameters (like UART baud rate), custom firmware developed by customer, or custom firmware developed by Bluegiga for the customer.
2 Block Diagram and Descriptions Flash BC05-MM UART/USB RAM Antenna Balanced filtter 2.4 GHz Radio Baseband DSP PIO I/O Audio In/Out MCU PCM/I2S/SPDIF Kalimba DSP SPI XTAL Reset circuitry Figure 1: Block diagram of WT32 BC05-MM The BlueCore05-MM is a single-chip radio and baseband IC for Bluetooth 2.4GHz systems. It provides a fully compliant Bluetooth system to v2.0+EDR of the specification for data and voice.
Synchronous Serial Interface This interface is a synchronous serial port interface (SPI) for interfacing with other digital devices. The SPI port can be used for system debugging. It can also be used for programming the Flash memory. UART This interface is a standard Universal Asynchronous Receiver Transmitter (UART) interface for communicating with other serial devices.
3 Electrical Characteristics 3.1 Absolute maximum ratings Storage temperature Operating temperature VDD_IO VDD_BAT VDD_CHG Terminal voltages Min -40 -30 -0.4 -0.4 -0.4 -0.4 Max 85 85 3.6 4.4 6.5 Vdd + 0,4 Unit °C °C V V V V The module should not continuously run under these conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. Table 1: Absolute maximum ratings 3.
3.3 Terminal characteristics Min Typ Max Unit VIL input logic level low -0.4 - 0.25xVDD V VIH input logic level high 0.625xVDD - Vdd + 0.3 V VOL output logic level low 0 - 0.125 V VOH output logic level high Reset terminal 0.75xVDD - VDD V 0.64 0.85 1.
3.4 Battery charger Battery charger VDD_CHG Charging mode (VDD_BAT rising to 4.2 V) (a) Supply current Maximum setting Battery trickle charge (b) (c) current Minimum setting (e) Headroom > 0.7 V Maximum battery fast (d) (c) charge current Headroom = 0.3 V Headroom > 0.7 V Minimum battery fast (d) (c) charge current Headroom = 0.
Stereo CODEC Analogue to Digital Converter Parameter Resolution Conditions Input Sample Rate, Fsample Fsample 8 kHz fin = 1kHz 11.025 kHz B/W = 20Hz→20kHz Signal to Noise A-Weighted 16 kHz Ratio, SNR THD+N < 1% 22.050 kHz 150mVpk-pk input 32 kHz 44.
3.5 Radio characteristics and general specifications Operating frequency range Specification Note (2400 ... 2483,5) MHz ISM Band Lower quard band 2 MHz Upper quard band 3,5 MHz Carrier frequency 2402 MHz ... 2480 MHz Modulation method Hopping Maximum data rate GFSK (1 Mbps) ∏/4 DQPSK (2Mbps) 8DQPSK (3Mbps) 1600 hops/s, 1 MHz channel space GFSK: Asynchronous, 723.2 kbps / 57.6 kbps Synchronous: 433.9 kbps / 433.9 kbps ∏/4 DQPSK: Asynchronous, 1448.5 kbps / 115.2 kbps Synchronous: 869.
3.6 Radio Characteristics Sensitivity (0.1% BER) Max output power (typical) WT32-A (*) DH1 3DH5 -87 dBm -81 dBm 0 dBm -1 dBm WT32-E (**) DH1 3DH5 -87 dBm -81 dBm 8 dBm 5 dBm (*) Measured from the antenna (**) Measured from the w-fl connector - In WT32-E the iWRAP firmware is configured by default for higer output power than in WT32-A 3.6.1 Radiation Pattern (WT32EK) o Peak gain = 1.
4 WT32 Pin Description RF RFTP VREG_ENA DGND DGND DGND AIO0 AIO1 PIO0 PIO1 PIO2 PIO3 USB_DUSB_D+ PIO9 PIO10 UART_RXD UART_TXD VDD_IO 50 AUDIO_OUT_P_LEFT AUDIO_OUT_N_LEFT AGND AUDIO_OUT_P_RIGHT AUDIO_OUT_N_RIGHT AUDIO_IN_N_LEFT AUDIO_IN_P_LEFT AGND AUDIO_IN_N_RIGHT AUDIO_IN_P_RIGHT MIC_BIAS AGND VDD_CHG VDD_BAT LED0 SPI_MOSI SPI_MISO SPI_CLK SPI_NCSB 31 DGND 1 17 PCM_CLK PCM_SYNC PCM_OUT PCM_IN PIO4 PIO5 PIO6 PIO7 PIO8 UART_NCTS UART_NRTS RESET DGND Figure 2: WT32 connection diagram (top view) NOT
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RFTP RTS# CTS# PIO8 PIO7 PIO6 PIO5 PIO4 PCM_IN PCM_OUT PCM_SYNC PCM_CLK DGND SPI_CS# SPI_CLK SPI_MISO SPI_MOSI LED0 VDD_BAT VDD_CHG AGND MIC_BIAS AUDIO_IN _P_RIGHT AUDIO_IN _N_RIGHT AGND AUDIO_IN _P_LEFT AUDIO_IN_N_LEFT AUDIO_OUT _N_RIGHT AUDIO_OUT _P_RIGHT AGND AUDIO_OUT_N_LEFT AUDIO_OUT_P_LEFT RF test point Table 8: WT32 device terminals 4.
VDD_BAT Input for an internal 1.8 V switched mode regulator combined with output of the internal battery charger. See chapter 5.3 for detailed description for the charger. When not powered from a battery, VDD_IO and VDD_BAT can be combined to a single 3.3 V supply voltage. VREG_ENA Enable pin for the internal 1,8 V regulator. This pin is only available with production version. With the engineering samples VREG_ENA is internally connected to VDD_BAT. VDD_CHG Charger input voltage.
PIO0 – PIO10 Programmable digital I/O lines. All PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. Configuration for each PIO line depends on the application. See section 10 “I/O parallel ports” for detailed descriptions for each terminal. Default configuration for all of the PIO lines is input with weak internal pull-up. AIO0 – AIO1 AIOs can be used to monitor analogue voltages such as a temperature sensor for the battery charger.
PCM_OUT A CMOS output with a weak internal pull-down. Used in the PCM (pulse code modulation) interface to 2 transmit digitized audio. The PCM interface is shared with the I S interface. PCM_IN A CMOS input with a weak internal pull-down. Used in the PCM interface to receive digitized audio. The 2 PCM interface is shared with the I S interface. PCM_CLK A bi-directional synchronous data clock signal pin with a weak internal pull-down. PCMC is used in the PCM interface to transmit or receive the CLK signal.
Right channel audio inputs. This dual audio input can be configured to be either single-ended or fully differential and programmed for either microphone or line input. Route differential pairs close to each other and use a solid dedicated audio ground plane for the audio signals. AUDIO_IN_P_LEFT and AUDIO_IN_N_LEFT Left channel audio input. ESD protection and layout considerations similar to right channel audio should be used. AUDIO_OUT_P_RIGHT and AUDIO_OUT_N_RIGHT Right channel audio output.
5 Power Control 5.1 Power Supply Configuration WT32 contains an internal battery charger and a switch mode regulator that is mainly used for internal blocks of the module. The module can be powered from a single 3.3 V supply provided that VDD_CHG is floating. Alternatively the module can be powered from a battery connected to VDD_BAT and using an external regulator for VDD_IO. 1.8 V to 3.3 V supply voltage for VDD_IO can be used to give desired signal levels for the digital interfaces of the module.
Figure 5: Example of how to make a power on/off button using latch feature of the internal regulators In Figure 5 the internal regulators are latched on at the rising edge, i.e when pressing SW1. One of the PIOs is configured to power hold thus keeping the external regulator on until shut down by pressing SW1 again. 5.3 Battery Charger The battery charger is a constant current / constant voltage charger circuit, and is suitable for lithium ion/polymer batteries only.
Fast Charge - Constant Voltage: entered when the battery has reached Vfloat, the charger switches mode to maintain the cell voltage at Vfloat voltage by adjusting the constant charge current. Standby: this is the state when the battery is fully charged and no charging takes place. When a voltage is applied to the charger input terminal VDD_CHG, and the battery is not fully charged, the charger will operate and a LED connected to the terminal LED0 will illuminate.
PCM_SYNC PCM_OUT PIO[10:0] Digital bi-directional with PD Digital tri-state output with PD Digital bi-directional with PU/PD Table 9: Pin states on reset 27 PD PD PD
6 Serial Interfaces 6.1 UART Interface WT32 Universal Asynchronous Receiver Transmitter (UART) interface provides a simple mechanism for communicating with other serial devices using the RS232 standard. The UART interface of WT32 uses voltage levels from 0 to VDD_IO and thus an external transceiver IC is required to meet the voltage level specifications of RS232.
tBRK UART_RX Figure 7: Break signal Table 11 shows a list of commonly used Baud rates and their associated values for the Persistent Store Key PSKEY_UART_BAUDRATE (0x204). There is no requirement to use these standard values. Any Baud rate within the supported range can be set in the Persistent Store Key according to the formula in Equation below. Baud Rate = PSKEY_UART_BAUD_RATE 0.
It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode is invoked. Therefore, it is not possible to have active Bluetooth links while operating the bypass mode. The current consumption for a device in UART Bypass Mode is equal to the values quoted for a device in standby mode.
6.2 USB Interface WT32 USB devices contain a full speed (12Mbits/s) USB interface that is capable of driving a USB cable directly. No external USB transceiver is required. To match the connection to the characteristic impedance of the USB cable, series resistors must be included to both of the signal lines. These should be of 1% tolerance and the value required may vary between 0 and 20 ohm with 10 ohm being nominal.
The terminal marked USB_ON can be any free PIO pin. The PIO pin selected must be registered by setting PSKEY_USB_PIO_VBUS to the corresponding pin number. In self powered mode, PSKEY_USB_PIO_PULLUP must be set to match with the PIO selected. Note: USB_ON is shared with WT32 PIO terminals (PIO2-PIO7). 6.2.3 Bus Powered Mode In bus powered mode, the application circuit draws its current from the 5V VBUS supply on the USB cable.
USB is visible to the user. Both control lines are shared with PIO pins and can be assigned to any PIO pin by setting the PS Keys PSKEY_USB_PIO_DETACH and PSKEY_USB_PIO_WAKEUP to the selected PIO number. USB_DETACH is an input that, when asserted high, causes WT32 to put USB_D- and USB_D+ in high impedance state and turns off the pull-up resistor on D+. This detaches the device from the bus and is logically equivalent to unplugging the device.
6.3 SPI Interface The synchronous serial port interface (SPI) is for interfacing with other digital devices. The SPI port can be used for system debugging. It can also be used for programming the Flash memory. SPI interface is connected by using the MOSI, MISO, CSB and CLK pins. SPI interface can not be used for any application purposes.
7 Audio Interfaces 7.1 Audio Interface The audio interface circuit consists of: Stereo audio CODEC Dual audio inputs and outputs A configurable PCM, I2S or SPDIF interface NOTE: the S/PDIF interface is not recommended for use at this time due to an issue with the lowlevel BlueCore05-MM firmware revision in use by iWRAP. The audio quality suffers because the left and right channels get out of sync. Figure 12 outlines the functional blocks of the interface.
7.2 Stereo Audio CODEC Interface The main features of the interface are: Stereo and mono analogue input for voice band and audio band Stereo and mono analogue output for voice band and audio band Support for stereo digital audio bus standards such as I2S Support for IEC-60958 standard stereo digital audio bus standards, e.g.
7.2.1 ADC The ADC consists of two second-order Sigma Delta converters allowing two separate channels that are identical in functionality, as shown in Figure 13Figure 14. Each ADC supports the following sample rates: 8kHz 11.025kHz 16kHz 22.05kHz 24kHz 32kHz 44.1kHz The ADC contains two gain stages for each channel, an analogue and a digital gain stage.
Figure 14: ADC analogue amplifier block diagram The second stage of the analogue amplifier shown in Figure 14 has a programmable gain with seven individual 3dB steps. In simple terms, by combining the 24dB gain selection of the microphone input with the seven individual 3dB gain steps, the overall range of the analogue amplifier is approximately 3dB to 42dB in 3dB steps. The overall gain control of the ADC is controlled by a VM function. See iWRAP user guide how to set the gain using iWRAP commands. 7.2.
10 11 12 13 14 15 -18 -14.5 -12 -8.5 -6 -2.5 Table 14: DAC digital gain rate selection The DAC analogue amplifier has a programmable gain with seven individual 3dB steps. The overall gain control of the DAC is controlled by a VM function.
Figure 16: Example circuit for SPDIF interface (Optical) 7.2.4 Microphone Input The audio-input is intended for use from 1μA@94dB SPL to about 10μA@94dB SPL. With biasing resistors R1 and R2 equal to 1kΩ, this requires microphones with sensitivity between about –40dBV and –60dBV. The MIC_BIAS is like any voltage regulator and requires a minimum load to maintain regulation. The MIC_BIAS will maintain regulation within the limits 0.2 - 1.53 mA depending on the bias current setting.
The input impedance at AUDIO_IN_N_LEFT, AUDIO_IN_P_LEFT, AUDIO_IN_N_RIGHT and AUDIO_IN_P_RIGHT is typically 6.0kΩ. C1 and C2 should be 150nF if bass roll-off is required to limit wind noise on the microphone. R1 sets the microphone load impedance and is normally in a range of 1 to 2 kΩ. R2, C3 and C4 improve the supply rejection by decoupling supply noise from the microphone. Values should be selected as required.
7.2.5 Line Input If the input analogue gain is set to less than 21dB, WT32 automatically selects line input mode. In line input mode, the first stage of the amplifier is automatically disabled, providing additional power saving. In line input mode, the input impedance varies from 6kΩ-30kΩ, depending on the volume setting. Figure 19 and Figure 20 show two circuits for line input operation and show connections for either differential or single-ended inputs.
7.2.6.1 Mono Operation Mono operation is a single-channel operation of the stereo CODEC. The left channel represents the single mono channel for audio in and audio out. In mono operation, the right channel is an auxilliary mono channel that may be used in dual mono channel operation. With single mono, the power consumption can be reduced by disabling the other channel. 7.2.6.2 Side Tone In some applications, it is necessary to implement a side tone.
7.3 Digital Audio Interface (I2S) 2 The digital audio interface supports the industry standard formats for I S, left-justified (LJ) or rightjustified(RJ). The interface shares the same pins as the PCM interface, which means that each audio bus is mutually exclusive in its usage. Table 18 lists these alternative functions. Figure 22 shows the timing diagram.
Figure 21: Digital audio interface modes The internal representation of audio samples within BlueCore5.Multimedia External is 16-bit and data on SD_OUT is limited to 16-bit per channel. Symbol - Parameter SCK Frequency WS Frequency Min - Typ - Max 6.
Figure 22: Digital audio interface slave timing Symbol - Parameter SCK Frequency WS Frequency Min - Typ - Max 6.
7.4 PCM Interface Pulse Code Modulation (PCM) is a standard method used to digitize audio (particularly voice) patterns for transmission over digital communication channels. Through its PCM interface, WT32 has hardware support for continual transmission and reception of PCM data, thus reducing processor overhead for wireless headset applications. WT32 offers a bi directional digital audio interface that routes directly into the baseband layer of the on-chip firmware.
PCM_OUT PCM_IN WT12 WTxx Up to 2048kHz PCM_CLK PCM_SYNC 8kHz Figure 25: WT32 as PCM slave 7.4.2 Long Frame Sync Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When WT32 is configured as PCM Master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8-bits long.
As with Long Frame Sync, WT32 samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge. 7.4.4 Multi Slot Operation More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO connections can be carried over any of the first four slots.
Sign extension PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 8-bit sample Figure 30: 16-bit slot with 8-bit companded sample and sign extension selected 8-bit sample PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Zeros padding Figure 31: 16-bit slot with 8-bit companded sample and zeros padding selected 3-bit sign extension PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 13-bit sample Figure 32: 16-bit slot with 13-bit linear sample and sign extension se
7.4.9 PCM Configuration The PCM configuration is set by using two PS Keys, PSKEY_PCM_CONFIG32 and PSKEY_PCM_LOW_JITTER_CONFIG. The following tables detail these PS Keys. The default for PSKEY_PCM_CONFIG32 key is 0x00800000, i.e. first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock with no tri-stating of PCM_OUT. PSKEY_PCM_LOW_JITTER_CONFIG is described in Table 23.
8 I/O Parallel Ports The Parallel Input Output (PIO) Port is a general-purpose I/O interface to WT32. The port consists of eleven programmable, bi-directional I/O lines, PIO[10:0]. Programmable I/O lines can be accessed either through an embedded application running on WT32 or through private channel or manufacturer-specific HCI commands. All PIO lines are configured as inputs with weak pull downs at reset. PIO[2] / USB_PULL_UP (1) The function depends on whether WT32 is a USB or UART capable version.
9 Software Stacks WT32 is supplied with Bluetooth v2.0 + EDR compliant stack firmware, which runs on the internal RISC microcontroller. The WT32 software architecture allows Bluetooth processing and the application program to be shared in different ways between the internal RISC microcontroller and an external host processor (if any). The upper layers of the Bluetooth stack (above HCI) can be run either on-chip or on the host processor. 9.
Notes: More details of iWRAP software and its features can be found from iWRAP User Guide, which can be downloaded from www.bluegiga.com. 9.2 VM Stack VM Application Software RFCOMM SDP L2CAP HCI LM LC 48kB RAM Baseband MCU USB Host I/O UART Host Radio I/O PCM I/O PCM Figure 35: WRAP THOR VM Stack The version of the stack firmware shown in Figure 35 requires no host processor (but can use a host processor for debugging etc.).
Sample applications to control PIO lines can also be written with BlueLab SDK and the VM for the HCI stack. Software Development WT32 Evaluation Kits are available to allow the evaluation of the WT32 hardware and software as well as a CSR BlueLab toolkit for developing on-chip and host software.
10 Enhanced Data Rate EDR has been introduced to provide 2x and optionally 3x data rates with minimal disruption to higher layers of the Bluetooth stack. CSR supports both of the new data rates, with WT32. WT32 is compliant with revision v2.0.E.2 of the specification. 10.1 Enhanced Data Rate Baseband At the baseband level, EDR uses the same 1.6kHz slot rate as basic data rate and therefore the packets can be 1, 3, or 5 slots long as per the basic data rate.
10.3 8DQPSK 8-state Differential Phase-Shift Keying Three bits determine phase shift between consecutive symbols.
11 Layout and Soldering Considerations 11.1 Soldering Recommendations WT32 is compatible with industrial standard reflow profile for Pb-free solders. The reflow profile used is dependent on the thermal mass of the entire populated PCB, heat transfer efficiency of the oven and particular type of solder paste used. Consult the datasheet of particular solder paste for profile configurations.
Figure 37: Recommended layout for the ground planes around the module. Figure 38: Bottom side layout of the module. Any via in the module can cause a short if placed directly above bare copper on a PCB.
12 WT32 Physical Dimensions Figure 39: Recommended PCB land pattern for WT32-A and WT32-E Figure 40: WT32 viewed from the top Bluegiga Technologies Oy Page 60 of 71
17.9 mm (+/- 0.15mm) 2.5 mm (+/- 0.1mm) 2.2 mm (+/- 0.1mm) 23.9 mm (+/- 0.15mm) 3.7 mm (+/- 0.1mm) 3.7 mm (+/- 0.1mm) 15.9 mm (+/- 0.1mm) 8.5 mm (+/- 0.
13 Package Figure 42: Carrier tape appearance and dimensions Bluegiga Technologies Oy Page 62 of 71
Figure 43: Reel appearance and dimensions Bluegiga Technologies Oy Page 63 of 71
14 Certifications WT32 is compliant to the following specifications. 14.1 Bluetooth WT32 module is Bluetooth qualified and listed as an end product. If not modified in any way, it is a complete Bluetooth entity, containing software and hardware functionality as well as the whole RF-part including the antenna. This practically translates to that if the module is used without modification of any kind, it does not need any Bluetooth approval work.
14.2 FCC Federal Communications Commission (FCC) Statement 15.21 You are cautioned that changes or modifications not expressly approved by the part responsible for compliance could void the user’s authority to operate the equipment. 15.105(b) This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.
14.3 CE WT32 meets the requirements of the standards below and hence fulfills the requirements of EMC Directive 89/336/EEC as amended by Directives 92/31/EEC and 93/68/EEC within CE marking requirement. Safety EN 60950-1:2006+A11:2009+A1:2010+A12:2011 Electromagnetic emission EN 301 489-17 V.2.1.
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15 RoHS Statement with a List of Banned Materials WT32 meets the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS) The following banned substances are not present in WT32, which is compliant with RoHS: Cadmium Lead Mercury Hexavalent chromium PBB (Polybrominated Bi-Phenyl) PBDE (Polybrominated Diphenyl Ether) Bluegiga Technologies Oy Page 70 of 71
16 Contact Information Sales: sales@bluegiga.com Technical support: support@bluegiga.com http://techforum.bluegiga.com Orders: orders@bluegiga.com WWW: www.bluegiga.com www.bluegiga.hk Head Office / Finland: Phone: +358-9-4355 060 Fax: +358-9-4355 0660 Sinikalliontie 5A 02630 ESPOO FINLAND Postal address / Finland: P.O. BOX 120 02631 ESPOO FINLAND Sales Office / USA: Phone: +1 770 291 2181 Fax: +1 770 291 2183 Bluegiga Technologies, Inc.
