User's Manual

Bluegiga Technologies Oy
Page 33 of 40
11 Reset
WT11i may be reset from several sources: RESET pin, power on reset, a UART break character or via
software configured watchdog timer. The RESET pin is an active high reset and is internally filtered using the
internal low frequency clock oscillator. A reset will be performed between 1.5 and 4.0ms following RESETB
being active. It is recommended that RESET be applied for a period greater than 5ms.
The power on reset occurs when the VDD_CORE supply internally to the module falls below typically 1.5V
and is released when VDD_CORE rises above typically 1.6V. At reset the digital I/O pins are set to inputs for
bidirectional pins and outputs are tri-state.
WT11i has an internal power on reset circuit which holds the module in reset until all the supply voltages have
stabilized. The reset pin must be either floating or connected to high impedance during power on in order for
the power on reset circuit to work properly. If the reset pin is not connected to high impedance during power
on, then one must ensure that the reset is kept active until all the supply voltages have stabilized to prevent
the flash memory getting corrupted.
11.1 Pin States on Reset
PIN NAME STATE
PIO
[
7:2
]
In
p
ut with weak
p
ull-down
PCM_OUT Tri-staed with weak
p
ull-down
PCM_IN In
p
ut with weak
p
ull-down
PCM_SYNC In
p
ut with weak
p
ull-down
PCM_CLK In
p
ut with weak
p
ull-down
UART_TX Out
p
ut tristated with weak
p
ull-u
p
UART_RX In
p
ut with weak
p
ull-down
UART_RTS Out
p
ut tristated with weak
p
ull-u
p
UART_CTS In
p
ut with weak
p
ull-down
USB+ In
p
ut with weak
p
ull-down
USB- In
p
ut with weak
p
ull-down
SPI_CSB In
p
ut with weak
p
ull-down
SPI_CLK In
p
ut with weak
p
ull-down
SPI_MOSI In
p
ut with weak
p
ull-down
SPI_MISO Out
p
ut tristated with weak
p
ull-down
AIO
[
1
]
Out
p
ut
,
drivin
g
low
Table 14: Pin States on Reset