User's Manual

Bluegiga Technologies Oy
Page 29 of 40
Figure 21: 16-bit Slot Length and Sample Formats
9.7 Additional Features
WT11i has a mute facility that forces PCM_OUT to be 0. In master mode, PCM_SYNC may also be forced to
0 while keeping PCM_CLK running which some codecs use to control power down.
9.8 PCM_CLK and PCM_SYNC Generation
WT11i has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is generating
these signals by DDS from BlueCore4-External internal 4MHz clock. Using this mode limits PCM_CLK to 128,
256 or 512kHz and PCM_SYNC to 8kHz. The second is generating PCM_CLK and PCM_SYNC by DDS from
an internal 48MHz clock (which allows a greater range of frequencies to be generated with low jitter but
consumes more power). This second method is selected by setting bit 48M_PCM_CLK_GEN_EN in
PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the length of PCM_SYNC can be
either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in PSKEY_PCM_CONFIG32.
The Equation XXX describes PCM_CLK frequency when being generated using the internal 48MHz clock: