User's Manual

2.2.3 GPIO Port Pins
The table below lists available Ports and corresponding Port pins in the WGM110 Module and the pads they can be routed to.
Table 2.4. Available GPIO Ports and Pins and Related Pads on the WGM110 Module
Pin → 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Port ↓
Port A PA6 PA2
Port B PB12 PB11
Port C PC15 PC14 PC13 PC9 PC1 PC0
Port D PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Port E PE15 PE14 PE13 PE12 PE11 PE10 PE2 PE1 PE0
Port F PF11 PF10 PF2 PF1 PF0
2.2.4 GPIO Input and Output Modes
The GPIO pins on the WGM110 Module can be configured as inputs (options are normal input with pull-up or pull-down or with pull-up
with filter or pull-down with filter), outputs (maximum output current 6 mA) or disabled (tristate). The default state of the GPIO pins after
reset is "disabled".
For more information on how to configure the GPIO pins and modes, see WGM110 API Reference Manual.
2.2.5 Interrupt Pins
All GPIO pins may be used as interrupts. WGM110 supports up to 14 asynchronous external pin interrupts with the following limitations:
• All pins with the same number are grouped together and multiplexed to trigger one interrupt.
• Pin 0 from any port cannot be used as an interrupt, because it is reserved for the Module’s internal operation.
• Pin 8 of Port A - F is not available for external use.
Example:
• If PB11 is used as an interrupt pin, then the use of Pin 11 of any other available port as an interrupt is not allowed (PE11 and PF11
cannot be used as an interrupt).
2.3 Debug and RF Test Pads
The table below indicates the pads available for debug and RF test connections.
Table 2.5. Debug and RF Test Pads
Debug and RF Test pads
Port Name RFPORT PF
Pad # 41 43 45 47 34 35
Pad # 50 52
Pad Name SPIMISO SPICLK SPIMOSI SPICS PF0 PF1
DEBUG
SWCLK •
SWDIO •
RF TEST
SPIMISO •
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Module Data Sheet
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