User's Manual

Bluegiga Technologies Oy
Page 19 of 41
In a 3.3V logic level host system all other supplies would usually be tied to the 3.3V supply, with a separate
regulator providing the 1.45-2.0V supply for the Wi-Fi core. A switch mode regulator with 1.5V output is
recommended for minimum power consumption. Please see the example schematic in this datasheet.
In a 1.8V logic level host system, all other supplies can be connected to the 1.8V supply rail except VDD_PA
which should be connected to a 2.7-4.8V supply.
The higher voltage supplies should be powered before or at the same time as the core supply line, i.e. the
VDD_REGIN should be powered up last. Powering the core first may lead to the GPIO and SDIO blocks
booting into an inaccessible state.
External high frequency bypassing for any the supply lines is not required, all supplies contain internal
capacitors. If the VDD_PA line is fed directly from a battery or there are concerns about the speed of the
regulator feeding it, a capacitor of around 100µF should be connected close to the module.
Note: All supply voltages and ground lines must be connected.
5.2 REGEN
The regulator enable pin REGEN is used to enable the WF111. REGEN enables the regulators of the digital
and analog core supply voltages.
The pin is active high, with a logic threshold of around 1V, and has a weak pull-down. REGEN can tolerate
voltages up to 2.0V, and may be connected directly to the internal voltage regulator input (VDD_REGIN) to
permanently enable the device. Part of the regulators can also be disabled by firmware in power saving
modes. The VDD_REGIN supply can also be externally switched off while leaving the other supply voltages
powered.
Cutting power to the core will fully shut down the module internal processors and returning power will cause a
power-on reset, requiring a full initialization of the module.
The REGEN pin will not disable system blocks not supplied by the core supply, meaning the coexistence
interface and the SDIO Function 0 are available even when the core is powered off.
5.3 RESET
WF111 may be reset from several sources: RESET pin, power-on reset, via software configured watchdog
timers as well as through the SDIO/CSPI host interface.
The RESET pin is an active low reset and is internally filtered using the internal low frequency clock oscillator.
A reset is performed between 1.5 and 4.0ms following RESET being active. It is recommended that RESET
be applied for a period greater than 5ms.
The power-on reset occurs when the core supply (generated by the internal 1.2V linear regulator) falls below
typically 1.05V and is released when core voltage rises above typically 1.10V. At reset regardless of the
source the digital I/O pins are set to a high impedance state with weak pull-downs, except RESET and
DEBUG_SPI_CS# which have a weak pull-up. The host connection interface is only reset by the RESET pin
or a power-on reset.
A power-on reset can be achieved through powering down the digital core by either externally cutting the
VDD_REGIN supply or giving a low pulse to the REGEN-pad. If REGEN is connected to the host system for
powering down the module, or a separate core power switch is implemented, the RESET pin can be tied
permanently to a supply voltage line.
Following a reset, WF111 automatically generates internally the clocks needed for safe boot-up of the internal
processors. The crystal oscillator is then configured by software with the correct input frequency.
Note: holding the RESET line low will not drive the module into a low power consumption mode, it
can’t be used as a power-off signal