User's Manual

Bluegiga Technologies Oy
Page 14 of 41
Figure 4: CSPI Register Read Cycle
4.1.3.4 CSPI register burst write cycle
Burst transfers are used to access the MMU buffers. They cannot be used to access registers. Burst
read/write cycles are selected by setting the nRegister/Burst bit in the command field to 1.
Burst transfers are byte orientated, have a minimum length of 0 bytes and a maximum length of 64kbytes.
Setting the length field to 0 results in no data being transferred to or from the MMU.
As with a register access, the command and address fields are transferred first. There is an optional length
field transferred after the address. The use of the length field is controlled by the LengthFieldPresent bit in the
Function 0 registers, which is cleared on reset.
Figure 5: CSPI Burst Write Cycle
4.1.3.5 CSPI register read cycle
Burst reads have a programmable amount of padding data that is returned by the slave. 0-15 bytes are
returned as defined in the BurstPadding register. Following this the Error byte is returned followed by the data.
Once the transfer has started, no further padding is needed.
A FIFO within SDIO_TOP will pre-fetch the data. The address is not retransmitted, and is auto-updated within
the slave.
The length field is transmitted if LengthFieldPresent in the Function 0 registers is set. In the absence of a
length field the CSB signal is used to indicate the end of the burst.
Figure 6: CSPI Burst Read Cycle
4.1.4 SDIO/CSPI deep-sleep control schemes
The module automatically enters deep sleep to minimize power consumption after a while of idling. Deep
sleep is the lowest power mode, where the processor, the internal reference (fast) clock, and much of the
digital and analogue hardware are shut down. The SDIO communication system however remains on, and is
clocked by the host system. During deep sleep only the function 0 is available, while attempts to access