Data Sheet

Bluegiga – A Silicon Labs Company 12
Power control
4.1 Power supply requirements
BT121 is powered by a single power supply input (VDD). Nominal input voltage is 3.3 VDC and input voltage
range 2.2 V to 3.6 V. If the module’s internal ADC and/or DAC functions are used minimum allowed power
supply voltage is 2.4V.
The VDD supply should be capable of supplying a peak current of at least 150 mA even though the average
current consumption of BT121 will be much less than that. External high frequency bypass capacitors are not
needed because the module contains the necessary power supply filtering capacitors.
Careful design of the layout and proper component selection are necessary to prevent switching noise from
appearing on the supply line. Such disturbances can be caused by on-board charge pump converters (e.g.
RS232 level shifters). Charge pump based converters tend to have strong switching spikes which are difficult
to filter out and may degrade RF performance. A ferrite chip can be added in series with the supply line close
to the module supply pin to reduce RF interference through the supply line.
There is a total of about 1.5 µF of ceramic capacitors on the VDD line inside the module. When using low drop
linear regulators to generate a regulated supply voltage for the VDD line, the stability of the regulator with the
low ESR provided by these capacitors should be checked. Many linear regulators and some switched mode
ones too are not stable when used with ceramic output capacitors. The regulator datasheets usually have
recommendations for output capacitor ESR range or they contain a stability curve to help select components
properly. A regulator designated as “stable with ceramic capacitors” is recommended.
4.2 Power saving functionality
BT121 contains two configurable power saving modes. The internal RTC (Real Time Clock) is usually kept
always running to avoid the long wake-up time associated with the internal 32 kHz crystal oscillator. The RTC
is always available to wake up the module.
4.2.1 Power mode 1
Power mode 1 is a shallow sleep state with all clocks and peripherals running but with the processor core
stopped. It is used automatically and has no impact on module performance and does not require special
considerations in user applications. See Table 3 on next page.
4.2.2 Power mode 2
Power mode 2 is a deep sleep state, in which most peripheral devices and system clocks are powered down.
The UART interfaces cannot operate without clocks, and instant communications with the host are not
possible. A separate wake-up command on the host UART or a PIO interrupt can be used to wake up the
module, or an RTC event. The radio can also cause a wake-up event. There is a short wake-up delay due to
the time required for the internal clocks to stabilize and because of this the module processor is not instantly
ready to receive data. See Table 3 on next page.