User's Manual

Bluegiga Technologies Oy
Page 24 of 31
8 Block diagram
BLE121LR is based on TI’s CC2541 chip. Embedded 32 MHz and 32.678 kHz crystals are used for clock
generation. Matched balun and low pass filter provide optimal radio performance with extremely low spurious
emissions.
Balun
+ LPF
Chip
antenna
I/O controller
CC2541
I/O
32 MHz
XTAL
32.768
kHz XTAL
Clock
Debug interface
8051 CPU core and memory arbitrator
Voltage regulator
SRAM
Flash
Analog
comparator
OPAMP
ADC
IRQ
controller
DMA
USART 0
USART 1
TIMER 1
TIMER 2
TIMER 3
TIMER 4
Radio arbiter
Radio registers
Link layer engine
SRAM
ModulatorDemodulator Synth
Receive Transmit
Frequenc
y
synthetisi
zer
Reset
Power-on reset
2V – 3.6V
Reset
PA/LNA
BPF
Figure 22: Simplified block diagram of BLE121LR
CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access buses (SFR,
DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit.
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points,
access of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR
registers. It is responsible for performing arbitration and sequencing between simultaneous memory accesses
to the same physical memory.
The SFR bus is a common bus that connects all hardware peripherals to the memory arbiter. The SFR bus
also provides access to the radio registers in the radio register bank, even though these are indeed mapped
into XDATA memory space.
The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces. The SRAM is
an ultralow-power SRAM that retains its contents even when the digital part is powered off (power modes 2
and 3).
The 256 KB flash block provides in-circuit programmable non-volatile program memory for the device, and
maps into the CODE and XDATA memory spaces.
Peripherals
Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise
programming.
A versatile five-channel DMA controller is available in the system, accesses memory using the XDATA
memory space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode,