User's Manual
Bluegiga Technologies Oy
Page 19 of 30
5 Design Guidelines
5.1 General Design Guidelines
LE113 can be used directly with a coin cell battery. Due to relatively high internal resistance of a coin cell
battery it is recommended to place a 100uF capacitor in parallel with the battery. The internal resistance of a
coin cell battery is initially in the range of 10 ohms but the resistance increases rapidly as the capacity is used.
Basically the higher the value of the capacitor the higher is the effective capacity of the battery and thus the
longer the life time for the application. The minimum value for the capacitor depends on the end application
and the maximum transmit power used. The leakage current of a 100uF capacitor is in the range of 0.5 uA to
3 uA and generally ceramic capacitors have lower leakage current than tantalum or aluminum electrolytic
capacitors.
Optionally TI’s TPS62730 can be used to reduce the current consumption during TX/RX and data processing
stages. TPS62730 is an ultra low power DC/DC converter with by-pass mode and will reduce the current
consumption during transmission nominally by ~20% when using 3V coin cell battery.
BLE113 Example Schematic
2012- 08 -03
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PR A
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Bluegiga Technologies Oy
-C1.0
15
REV:SIZE:CODE:
DRAWN:DATED:
DATED:CHECKED:
QUALITY CONTROL:DATED:
DATED:RELEASED:
COM PANY:
TITLE:
DRAWING NO:
SHEET: OFSCALE:
REVISION RECORD
APPROVED:ECO NO:LTR DATE:
123456
D
C
B
A
C
D
B
A
PROGRAMMING INTERFACE
P1_0 and P1_1 require external pull-up or pull-down
resistor if configured as inputs
C14
10 0u F/16V/10%/TAN
12
U 4
BATTER YH OLD ER _SMD _C R2032
1
STAT
2
SW
3
VIN
4
GN D
5
ON/BYP
6
VOUT
U5
TPS62730
C10
2.2uF/10V/X5R
C11
2.2uF/10V/X5R
L1
2.2µ H±2 0%, 13 0m A, 0 .43 ohm
1
2
R4
NP
C5
0.47uF/6.3V/X5 R
C6
0.47uF/6.3V/X5 R
1
2
4
3
SW1
1
2
R1
10K, 5 0V, 0.0 63W
1
GND
2
GND
3
GND
4
GND
5
GND
6
GND
7
GND
8
AVDD
9
P2_2
10
P2_1
11
P2_0
12
P1_7
13
P1_6
14
SCL
15
SDA
16
NC
17
DVDD
18
GND
19
P1_5
20
P1_4
21
P1_3
22
P1_2
23
P1_1
24
P1_0
25
GND
26
P0_7
27
P0_6
28
P0_5
29
P0_4
30
P0_3
31
P0_2
32
P0_1
33
P0_0
34
RESET
35
NC
36
GND
M OD2
BLE11 X_P2
1 2
R16
4.7K, 50V, 0 .06 3W
1 2
R17
4.7K, 50V, 0 .06 3W
1
VDDIO
2
BYP
3
NC
4
SCL
5
GND
6
SDA
7
SA0
8
NC
9
INT2
10
GND
11
INT1
12
GND
13
NC
14
VDD
15
NC
16
NC
U2
M MA8 451Q
C7
4. 7uF/4V/ X5R/10%
C8
0. 1uF/10 V/X5R
1
3
5
2
4
6
78
91 0
J 1
HEADER_2 X5_SM D_1.27M M
1
2
R2
10K, 5 0V, 0.0 63W
1
2
R21
10K, 5 0V, 0.0 63W
VBAT
P1_7 /DCDC
2V...3V3_M OD
2V...3V3_MOD
P2_2 /PROG
P2_1 /PROG
P1_7 /DCDC
SCL
SDA
2V...3V3_M OD
SCL
SDA
P2_2 /PROG
2V...3V3_SW
P2_1 /PROG
RESET_N
2V...3V3_M OD
Figure 11: Example schematic for BLE113 with a coin cell battery, TPS62730 DCDC converter and an
I2C accelerometer
5.2 Layout Guide Lines
Use good layout practices to avoid excessive noise coupling to supply voltage traces or sensitive analog
signal traces. If using overlapping ground planes use stitching vias separated by max 3 mm to avoid emission
from the edges of the PCB. Connect all the GND pins directly to a solid GND plane and make sure that there
is a low impedance path for the return current following the signal and supply traces all the way from start to
the end.
A good practice is to dedicate one of the inner layers to a solid GND plane and one of the inner layers to
supply voltage planes and traces and route all the signals on top and bottom layers of the PCB. This
arrangement will make sure that any return current follows the forward current as close as possible and any
loops are minimized.