User's Manual

Bluegiga Technologies Oy
Preliminary – information subject to change
Page 20 of 27
6 Block diagram
BLE112 is based on TI’s CC2540 chip. Embedded 32 MHz and 32.678 kHz crystals are used for clock
generation. Matched balun and low pass filter provide optimal radio performance with extremely low spurious
emissions. Small ceramic chip antenna gives good radiation efficiency even when the module is used in
layouts with very limited space.
I/Ocontroller
CC2540
I/O
32MHz
XTAL
32.768
kHzXTAL
Clock
Debuginterface
8051CPUcoreandmemoryarbitrator
Voltageregulator
SRAM
Flash
Analogcomparator
OPAMP
ADC
IRQcontroller DMA
USB
USART0
USART1
TIMER1
TIMER2
TIMER3
TIMER4
Radioarbiter
Radioregisters
Linklayerengine
SRAM
ModulatorDemodulator Synth
Receive Transmit
Frequency
synthetisizer
Balun+
LPF
Ant
Reset
Power‐onreset
2V–3.6V
Reset
Figure 16: Simplified block diagram of BLE112
CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access buses (SFR,
DATA, and CODE/XDATA), a debug interface, and an 18-input extended interrupt unit.
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points,
access of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR
registers. It is responsible for performing arbitration and sequencing between simultaneous memory accesses
to the same physical memory.