User's Manual

7.2 Alternate Functionality Pinout
A wide
selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alter-
nate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 7.3. Alternate functionality overview
Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
ACMP0_O
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13 15: PC10 16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
Analog comparator
ACMP0, digital out-
put.
ACMP1_O
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13 15: PC10 16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
Analog comparator
ACMP1, digital out-
put.
ADC0_EXTN
0: PA0 Analog to digital
converter ADC0 ex-
ternal reference in-
put negative pin
ADC0_EXTP
0: PA1 Analog to digital
converter ADC0 ex-
ternal reference in-
put positive pin
CMU_CLK0
0: PA1
3: PC11
5: PD14
6: PF2
Clock Management
Unit, clock output
number 0.
CMU_CLK1
0: PA0
3: PC10
5: PD15
6: PF3
Clock Management
Unit, clock output
number 1.
DBG_SWCLKTCK
0: PF0
Debug-interface
Serial Wire clock
input and JTAG
Test Clock.
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull down.
DBG_SWDIOTMS
0: PF1
Debug-interface
Serial Wire data in-
put / output and
JTAG Test Mode
Select.
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull up.
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Smart Module Data Sheet
Pin Definitions
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