Data Sheet

Bluegiga Technologies Oy
Page 37 of 52
6.11 HSADC (High-Speed ADC)
Function
Value
Input sampling capacitance (Cs)
1.0pF typical
Resolution
12 bits
Maximum sampling rate
2MHz
DC input voltage
0.5 — VDDA-0.5
Power-up time
1 sample cycles
Table 48: HSADC
The processor contains a high speed, high resolution analog to digital converter which can be used when the
lower resolution ADCs do not provide enough sampling speed or resolution.
For more information refer to refer to the i.MX28 Applications Processor Reference Manual.
6.12 JTAG
Pin#
Function
Net name
Note
118
Mode
LCD_D1
LCD_D1=HIGH: CPU is ready, waiting for JTAG
connection
177
JTAG return clock (Factory
reset)
JTAG_RTCK*
During normal operation, this pin is reserved for use
as a factory reset button by the software.
178
JTAG test clock
JTAG_TCK
179
JTAG test data in
JTAG_TDI
180
JTAG test data out
JTAG_TDO
181
JTAG test mode select
JTAG_TMS
182
JTAG test reset
JTAG_TRST
183
Ground
GND
184
JTAG enable boundary scan
DEBUG**
DEBUG=0: JTAG interface works for boundary scan.
DEBUG=1: JTAG interface works for ARM
debugging.
Table 49: JTAG pins
* Most JTAG adapters do not use the Return Test Clock in which case it can be used for other purposes. E.g.
on the APX4 reference design this pin is used for Factory Reset button.
** DEBUG pin is pulled down inside CPU. Leave unconnected for ordinary boundary scan.