User`s manual

58
JP41 & JP42 Clock Skew
Controls clock skew for:
Sysclk, SDRAM
Off-board clocks.
CPLD Programming Port
JP2 System CPLD (6 pin SIP)
JP30 PCI CPLD (6 pin SIP)
DIP Switches
S1-1
S1-2
S1-3
S1-4
S2-1 SH3's PTL0
S2-2 SH3's PTL1
S2-3 SH3's PTL2
S2-4 SH3's PTL3
Expansion Bus
J10 140 pin connector (Hitachi Tahoe daughter board)
JP37 200 pin connector (Hitachi daughter boards)
JTAG / E10A Interface
JP15 Harp JTAG (JP28) Enable
In = Enable Harp JTAG
Out = Disable Harp JTAG
JP18 JTAG2 Enable PCI Path
In = Enable PCI path
Out = ?
JP21 JTAG3 PCI Bypass
In = PCI Bypass
Out = ?
JP26 Local JTAG
1-2 = Enable local JTAG
2-3 = Bypass
JP27 Hitachi JTAG (14 pin DIP connector)
JP28 Harp JTAG (6 pin)
1 = GND 4 = RST#
2 = TDO 5 = TMS
3 = TDI 6 = CLK