User`s manual

Individual Memory Control Register (MCR)

The individual memory control register (MCR) is a 16-bit read/write register that specifies

RAS and CAS timing and burst control for DRAM (area 3 only), SDRAM (areas 2 and 3),

specifies address multiplexing, and controls refresh. This enables direct connection of DRAM

and SDRAM without external circuits.

The MCR is initialized to H'0000 by power-on resets, but is not initialized by manual resets or

standby mode. The bits TPC1–TPC0, RCD1–RCD0, TRWL1–TRWL0, TRAS1–TRAS0,

RASD, BE, SZ, AMX1–AMX0, and EDOMODE are written to at the initialization after a

power-on reset and are not then modified again. When RFSH and RMODE are written to,

write the same values to the other bits. When using DRAM, and SDRAM, do not access areas

2 and 3 until this register is initialized.

SDRAM Mode Register (SDMR3)

The synchronous DRAM mode register (SDMR3) is a write-only virtual 16-bit register that is

written to via the synchronous DRAM address bus, and sets the mode of the area 3

synchronous DRAM.

SDRAM Mode Register SDMR3 0x8C0

Refresh Timer Control/Status Register (RTSCR)

Refresh timer control/status register (RTSCR) is a 16-bit read/write register that specifies the

refresh cycle, whether to generate an interrupt. It is initialized to H'0000 by a power-on reset,

but is not initialized by a manual reset or standby mode.

Note: Writing to the RTCSR differs from that to general registers to ensure the RTCSR is not

rewritten incorrectly. Use the word-transfer instruction to set the upper byte as B'10100101

and the lower byte as the write data.

Refresh Timer Control/Status Register RTSCR 0xA50C

Individual memory control MCR H'FFFFFF68 0xd72c

bit15-14: RAS Precharge Time = 4 cycles ( 1 1 )

bit13-12: RAS–CAS Delay = 2 cycles ( 0 1 )

bit11-10: Write-Precharge Delay = 2 cycles ( 0 1 )

bit9-8: CAS -Before-RAS Refresh RAS Assert Time=4cyc( 11)

bit7: Auto precharge ( 0 )

bit6: Burst Disabled ( 0 )

bit5-4: Address Multiplex 8Mx8 ( 1 0 )

bit3: Address Multiplex 8Mx8 ( 1 )

bit2: Refresh Control ( 1 )

bit1: CAS before RAS refresh ( 0 )

bit0: normal SDRAM ( 0 )