User`s manual

39
Table 18: SDRAM 64MB tests
Test Number Data Width Test/Data Written
1 32 bit Write Background of 0xFFFFFFFF and then walk
through and read background, write foreground of
0x00000000, then read foreground
2 32 bit Write Background of 0x00000000 and then walk
through and read background, write foreground of
0xFFFFFFFF, then read foreground
3 32 bit Write Background of 0xAAAAAAAA and then
walk through and read background, write
foreground of 0x55555555, then read foreground
4 32 bit Write Background of 0x55555555 and then walk
through and read background, write foreground of
0xAAAAAAAA, then read foreground
5 32 bit Write Incrementing Address through memory. Then
read memory and compare address
6 8 bit Write Incrementing Address through memory (byte
write). Then read memory and compare address
(byte read).
Debug Serial Port
Table 19: Debug Serial Port Resource Assignment
Signal Source I/O Port Notes
DTR2 7709A/7729 SCK1/SCPT3
RXD2 7709A/7729 RXD2/SCPT4
TXD2 7709A/7729 TXD2/SCPT4
DSR2 7709A/7729 SCK2/SCPT5
RTS2 7709A/7729 RTS2/SCPT6
CTS2 7709A/7729 CTS2/IRQ5/SCPT7
DCD2 7709A/7729 RAS2L/PTJ1
RI2 7709A/7729 PTG4 R/O