User`s manual

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Section 5 Programmer’s Guide
Memory Map
The SH7729 Key West Demonstration Platform is a stand-alone computing system. The SH3
MCU supports up to seven external chip select spaces: Boot Flash (EPROM), SDRAM, PCI,
Ethernet, Parallel Port, PCMCIA, and daughter card interface. The flash-memory resource can be
erased and reprogrammed in 64 Kbytes blocks and provides protection for bootstrap program
storage.
The SH-3 processor has a fixed partition of address space. It supports six external 64MB segments
or Areas in physical address space and one internal segment. The decode for these address areas is
hard coded and available from the processor as six Chip Selects (CSn).
System Overview
Figure 3 : Overview of Address Space Assignments
Boot ROM/Flash
Internal I/O
PCI Aperture
SDRAM
Intelligent Peripheral Controller
PCI Aperture 1/PCMCIA Socket 1
PCI Aperture 2/PCMCIA Socket 0
Area 0: 0x00000000
Area 1: 0x04000000
Area 2: 0x08000000
Area 3: 0x0C000000
Area 4: 0x10000000
Area 5: 0x14000000
Area 6: 0x18000000
Internal Registers of Intelligent Peripheral
Controller
Jumper select between PCI aperture and
PCMCIA socket
Jumper select between PCI aperture and
PCMCIA socket
Reserved for internal 7709 registers
Jumper Selectable between Flash and PCI
Aperture
Table 12 System Address Space Definition
Area Base Address Upper Limit Phys. Addr.
A28-A26
Size 7709A/7729 Chip
Select
Word Size* Function