Specifications

Product Technical Specification & Customer Design Guidelines
38 Proprietary and Confidential - Contents subject to change 4114634
I2S
The I2S can be used to transfer serial digital audio to/from an external stereo
DAC/ADC. Interface implementation details include:
• Modes: Master (Slave mode is not supported)
• Sampling rates: 48 kHz
• Bits per frame: 16
• Bit clock: 1536 kHz
Figure 3-11 and Tab l e 3- 8 describe the I2S interface timing (per the Philips I2S
bus timing specification).
Figure 3-11: I2S transmitter timing
T(sync_offset) PCM_SYNC offset time to
PCM_CLK falling
- 122 - ns
T(sudin) PCM_DIN setup time before falling
edge of PCM_CLK
60 - - ns
T(hdin) PCM_DIN hold time after falling
edge of PCM_CLK
60 - - ns
T(pdout) Delay from PCM_CLK rising to
PCM_DOUT valid
- - 60 ns
T(zdout) Delay from PCM_CLK falling to
PCM_DOUT HIGH-Z
- - 60 ns
1. Maximum PCM clock rate is 2.048 MHz.
Table 3-7: PCM Timing
1
(Continued)
Parameter Description Min Typ Max Unit
SCK
SD and WS
T
t(hc) t(lc)
t(dtr) t(htr)
Table 3-8: I2S master transmitter timing
1,2
Parameter Description Condition Min Typ Max Unit
T Clock period I2S requirement: min T=293 293 326 359 ns
t(hc) Clock high I2S requirement: min > 0.35T 120 - - ns
t(lc) Clock low I2S requirement: min > 0.35T 120 - - ns
t(dtr) Delay I2S requirement: Max < 0.8T - - 250 ns
t(htr) Hold time I2S requirement: min > 0 1-- - - ns
1. Bit clock: 1536 KHz (±10%)
2. Sample rate: 48 KHz (16 bits per sample)