Specifications

Electrical Specifications
Rev 8 Apr.14 Proprietary and Confidential - Contents subject to change 37
PCM
The PCM interface implementation details include:
• Modes: Master and slave
• Sampling rates: 8 kHz, 16 kHz
• Audio compression formats: Linear, µ-law, A-Law
• Padding: Disabled, enabled
• Bits per frame: 8, 16, 32, 64, 128, 256
• Bit frequency: (Sampling rate * Bits per frame)
Figure 3-8, Figure 3-9 and Figure 3-10, and Table 3 - 7 below describe the PCM
interface timing.
Figure 3-8: PCM_SYNC timing
Figure 3-9: Timing—PCM_CODEC to Module
Figure 3-10: Timing—Module to PCM_CODEC
Table 3-7: PCM Timing
1
Parameter Description Min Typ Max Unit
T(sync) PCM_FS cycle time - 125 - µs
T(synch) PCM_FS high time - 488 - ns
T(syncl) PCM_FS low time - 124.5 - µs
T(clk) PCM_CLK cycle time - 488 - ns
T(clkh) PCM_CLK high time - 244 - ns
T(clkl) PCM_CLK low time - 244 - ns
PCM_SYNC
t(sync)
t(synca) t(syncd)
PCM_CLK
MSB LSB
t(clk)
t(clkh)
t(tckl)
t(susync) t(hsync)
t(sudin) t(hdin)
PCM_SYNC
PCM_DIN
PCM_CLK
t(clk)
t(clkh)
t(tckl)
t(susync) t(hsync)
t(pdout)
t(pdout)
PCM_SYNC
PCM_DOUT
MSB LSB
t(zdout)