Specifications

Rev 1 Dec.10 Proprietary and Confidential - Specifications subject to change 35
8 EXT_USIM_DATA USIM I/O pin Input High
(1.8 V)
1.26 2.10 Digital
Input Low
(1.8 V)
0.00 0.40
Output High
(1.8 V)
1.26 1.80 2.10
Output Low
(1.8 V)
0.00 0.40
Input High
(3.0 V)
2.10 3.30
Input Low
(3.0 V)
0.00 0.60
Output High
(3.0 V)
2.10 3.00 3.30
Output Low
(3.0 V)
0.00 0.60
9 EXT_USIM_CLK USIM clock Output High
(1.8V)
1.26 1.80 2.10 Digital
Output Low
(1.8V)
0.00 0.40
Output High
(3.0V)
2.10 3.00 3.30
Output Low
(3.0V)
0.00 0.60
10 VREF_1V8 1.8 V LDO High
(when
module is on)
Output 1.62 1.8 1.98 Power
11 SPI_CS_N SPI chip select Low Output High 1.35 - 1.8 Digital
Output Low 0 - 0.45
12 SPI_CLK SPI clock Output High 1.35 - 1.8 Digital
Output Low 0 - 0.45
13 SPI_DATA_MOSI SPI Master Output /
Slave Input data pin
Output High 1.35 - 1.8 Digital
Output Low 0 - 0.45
14 SPI_DATA_MISO SPI Master Input /
Slave Output data pin
Input High 1.17 - 2.1 Digital
Input Low -0.3 - 0.63
15 NC No connect
16 NC No connect
17 NC No connect
18 NC No connect
Table 4-2: SL808X LGA pad pin assignments (Continued)
a
Pin Signal name Description
Active
state
Input / Output
(Direction to
module)
Voltage (V)
Min
b
Typ
b
Max
b
Type