Technical data

SYSTEM CONNECTOR INTERFACE
49
LZT 123 8020 R1A
Note! If the voltage of the signal to be measured may be altered by
the internal circuitry of this shared signal, then the application
should use ADC1, ADC2 or ADC3 instead.
2.75V
ADC
100kΩ
10kΩ
A
2.75V
Analog IC
10#/ADC#
1MΩ
1nF
Figure 5.12 Input circuit for combined digital I/O and ADC pins
5.17 External I
2
C Serial Control Bus
Pin Signal Dir Description
29 SDA I/O I
2
C serial data
30 SCL O I
2
C serial clock
The I
2
C bus is controlled by embedded application script
commands it is not available in the GM47r5.
The external I
2
C bus consists of two signals, SDA and SCL.
This bus is isolated from the radio device’s internal I
2
C bus to
ensure proper operation of the radio device, in the event of the
external I
2
C bus being damaged.
The electrical characteristics are shown below.
Parameter Min. Typ. Max. Units
Frequency I
2
C CLK 81.25 400 kHz
High or low I
2
C CLK 1.2 µs
Delay time after falling edge of I
2
C
CLK
308 308-
1230
ns
Transmit operation
Hold time after falling edge of I
2
C CLK 0 ns
Frequency I
2
C CLK 400 kHz
High or low I
2
C CLK 1.2 µs
Receive o
p
eration
Delay time after falling edge of I
2
C
CLK
100 ns