Technical data

SYSTEM CONNECTOR INTERFACE
36
LZT 123 8020 R1A
PCM Timing Diagrams
The PCM timing is shown in Figure 5.8below and it is seen that
the CPU has 45 µs to serve an interrupt and setup data
channels. Data is sent on the falling edge of the sync pulse.
The data bits in PCMULD and PCMDLD are aligned so that the
MSB in each word occurs on the same clock edge as shown in
Figure 5.9.
Figure 5.8 16-bit word within 24-bit frame
PCM signal timing is shown in Figure 5.9. The signals
characteristics are described in the tables following Figure 5.9.
t
PSS
t
PSH
t
DSL
t
DSH
t
PDLP
Figure 5.9 PCM Timing Diagram
Name Description Typ. Unit
t
PSS
PCMSYN (setup) to PCMCLK (fall) 2.5 µs
t
PSH
PCMSYN pulse length 5 µs
t
DSL
PCMI (setup) to PCMCLK (fall) 2.5 µs
t
DSH
PCMI (hold) from PCMCLK (fall) 2.5 µs
t
PDLP
PCMO valid from PCMCLK (rise) 2.5 µs
Name Description Typ. Unit
F
PCMCLK
PCM clock frequency 200 kHz