Specifications

WA_DEV_FEX20_PTS_004 Rev 001 June 30, 2010 26
Expansion Card Product Technical
Specification
Interfaces
4.4.2. I
2
C Bus
The I
2
C interface includes a clock signal (SCL) and a data signal (SDA) which complies with
100Kbit/s–standard interface (standard mode: s-mode).
The I
2
C bus is always in master mode operation.
The maximum speed transfer is 400Kbit/s (fast mode: f-mode).
For more information on the I
2
C bus, see document [17] “I2C Bus Specification”, Version 2.0, Philips
Semiconductor 1998.
4.4.2.1. Pin Description
Table 16: I
2
C Bus Pin Description
Pin
Number
Signal
I/O
I/O Type
Reset State
Description
Multiplexed
With
28
SCL
O
Open drain
Z
Serial Clock
GPIO26
30
SDA
I/O
Open drain
Z
Serial Data
GPIO27
Refer to section 4.2 Electrical Information for Digital I/O for open drain, 2V8 and 1V8 voltage
characteristics and reset state definitions.
4.4.2.2. Waveforms
The figure below shows the I
2
C bus waveforms in master mode configuration.
Figure 6. I
2
C Timing Diagram (Master)
Table 17: I
2
C Bus AC Characteristics
Signal
Description
Minimum
Typical
Maximum
Unit
SCL-freq
I²C clock frequency
100
400
KHz
T-start
Hold time START condition
0.6
µs