Specifications

WA_DEV_FEX20_PTS_004 Rev 001 June 30, 2010 25
Expansion Card Product Technical
Specification
Interfaces
Table 14: SPI2 Bus Pin Description
Pin
Number
Signal
I/O
I/O Type
Reset State
Description
Multiplexed
With
19
SPI2-CLK
O
2V8
Z
SPI Serial Clock
GPIO32
20
SPI2-IO
I/O
2V8
Z
SPI Serial input/output
GPIO33
22
SP2-I
I
2V8
Z
SPI Serial input
GPIO34
21
~SPI2-CS
O
2V8
Z
SPI Enable
GPIO35
Refer to section 4.2 Electrical Information for Digital I/O for open drain, 2V8 and 1V8 voltage
characteristics and reset state definitions.
4.4.1.4. Waveforms
The figure below shows the waveforms for SPI transfers with a 4-wire configuration in master mode 0
(chip select is not represented).
Figure 5. SPI Timing Diagram (Mode 0, Master, 4 wires)
Table 15: SPI Bus AC Characteristics
Signal
Description
Minimum
Typical
Maximum
Unit
CLK-cycle
SPI clock frequency
0.1015
13
MHz
Data-OUT delay
Data-OUT ready delay time
10
ns
Data-IN-setup
Data-IN setup time
2
ns
Data-OUT-hold
Data-OUT hold time
2
ns