Specifications
XT65/XT75 Hardware Interface Description
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XT65_XT75_HD_v01.001 Page 9 of 133 2007-1-8
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Preceding document: "XT65/XT75 Hardware Interface Description" Version 00.144
New document: "XT65/XT75 Hardware Interface Description" Version 01.001
Preceding document: "XT65/XT75 Hardware Interface Description" Version 00.130
New document: "XT65/XT75 Hardware Interface Description" Version 00.144
Preceding document: "XT65/XT75 Hardware Interface Description" Version 00.071
New document: "XT65/XT75 Hardware Interface Description" Version 00.130
Chapter What is new
3.15 New section Analog-to-Digital Converter (ADC). Removed corresponding table footnote
from Table 29.
3.3.3.2 Updated remark on how to minimize leakage current.
3.8 Modified the RTC backup section to include the GPS receiver’s separate RTC.
6.2 Added information on GSM-GPS antenna coupling.
7.1 Added GPS antenna ratings (Table 22).
7.7 Updated average current consumption for GSM calls in Table 32 and Table 33.
8.3 Added note regarding inverse polarity protection for board-to-board connector.
11.4 New Appendix section Mounting Advice Sheet.
Chapter What is new
2.1, 4.1.4 Modified values for GPS position accuracy.
3.5.4, 11.3 Added information related to specific types of batteries and specific vendors.
3.10 Added note in Figure 16 on availability of signal pins under Java. See also Chapter 9.
4.4 Added remark on power saving while module is set to SLEEP mode 9 (AT+CFUN=9).
7.2 Added new temperature table (Table 25) listing ambient temerature values with forced
air circulation.
7.6 New chapter Power Supply for Active GPS Antenna listing power supply details for GPS
antenna.
7.7 Modified power supply values in Table 31.
7.8.3 Table 35: Changed output voltage values for EP output signal to Vpp = 4.2V.
Chapter What is new
1.3.1 Added note on PTCRB approval for applications used in the USA.
2.1 Available FFS memory for Java programs is 1.2MB.
Added GPS sensitivity as feature.
3.3.1.1 Added reference to Section 3.3.1.6 in Figure 5 and Figure 6.
3.14.4.1 Specified jitter from an ideal 512kHz clock. Modified master mode description.
3.14.4.2 Modified slave mode description.