Specifications

XT65/XT75 Hardware Interface Description
3.13 SPI Interface
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XT65_XT75_HD_v01.001 Page 57 of 133 2007-1-8
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3.13 SPI Interface
The SPI (serial peripheral interface) is a synchronous serial interface for control and data transfer between the
XT65/XT75 module and the connected application. Only one application can be connected to the module’s SPI.
The interface supports transmission rates up to 6.5Mbit/s. It consists of four lines, the two data lines SPIDI/
SPIDO, the clock line SPICLK and the chip select line SPICS.
The XT65/XT75 module acts as a single master device, e.g. the clock SPICLK is driven by module. Whenever
the SPICS pin is in a low state, the SPI bus is activated and data can be transferred from the module and vice
versa. The SPI interface uses two independent lines for data input (SPIDI) and data output (SPIDO).
Figure 20: SPI interface
To configure and activate the SPI bus use the AT^SSPI command. If the SPI bus is active the two lines I2CCLK
and I2DAT are locked for use as I2C lines. Detailed information on the AT^SSPI command as well explanations
on the SPI modes required for data transmission can be found in [1].
In general, SPI supports four operation modes. The modes are different in clock phase and clock polarity. The
module’s SPI mode can be configured by using the AT command AT^SSPI. Make sure the module and the con-
nected slave device works with the same SPI mode.
Figure 21 shows the characteristics of the four SPI modes. The SPI modes 0 and 3 are the most common used
modes.
For electrical characteristics please refer to Table 29.