Specifications

XT65/XT75 Hardware Interface Description
3.3 Power-Up / Power-Down Scenarios
s
XT65_XT75_HD_v01.001 Page 35 of 133 2007-1-8
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3.3.2 Signal States after Startup
Table 6 describes the various states each interface pin passes through after startup and during operation.
As shown in Figure 5 and Figure 6 the pins are in undefined state while the module is initializing. Once the startup
initialization has completed, i.e. when CTS is high and the software is running, all pins are in defined state. The
state of several pins will change again once the respective interface is activated or configured by AT command.
Table 6: Signal states
Signal name Undefined state
during startup
Defined state after
initialization
Active state after configuration by AT
command
GPIO SPI I
2
C DAI
SYNC O, L O, O
CCIN I, PU(100k) I, PU(100k)
CCRST O, L O, L
CCIO O, L O, L
CCCLK O, L O, L
CCVCC O, L 2.9V
RXD0 I, PU O, H
TXD0 I, PU I, PD(330k)
CTS0 O, L O, L
RTS0 I, PU I, PD(330k)
DTR0 I, PU I
DCD0 O, L O, H
DSR0 O, L O, H
RING0 I, PU O, H
SPIDI I Tristate I Tristate
SPICS I O, H O, L Tristate
I2CDAT_SPIDO I Tristate O, L/H IO
I2CCLK_SPICLK I Tristate O, L/H O, OD
GPIO1 I, PU Tristate IO
GPIO2 I, PU Tristate IO
GPIO3 I, PU Tristate IO
GPIO4 I, PD Tristate IO
GPIO5 O, L Tristate IO
GPIO6 I Tristate IO
GPIO7 I Tristate IO
GPIO8 O, L Tristate IO
GPIO9 I Tristate IO
GPIO10 I Tristate IO
DAC_OUT O, L O, L
DAI0 I Tristate O, L