Specifications

XT55 Hardware Interface Description
Confidential / Preliminary
s
mo b i l e
XT55_hd_v00.02 Page 75 of 116 17.03.2004
Figure 31: Example of LED circuit
4.8 Receiver architecture
The XT55 GPS receiver is a product that features the SiRFstarII-Low Power chipset. This
complete 12 channel, WAAS-enabled GPS receiver provides a vastly superior position
accuracy performance in a much smaller package. The SiRFstarII architecture builds on the
high-performance SiRFstarI core, adding an acquisition accelerator, differential GPS
processor, multipath mitigation hardware and satellite-tracking engine. The XT55 GPS
receiver delivers major advancements in GPS performance, accuracy, integration,
computing power and flexibility.
Antenna input
LNA
RF
Filter
GRF2i/LP
RF
Front-End
GSP2e/LP
Signal
Processor
XTAL
Data Bus
Address Bus
GPS-Data
AGC
Clock
Reset IC
FLASH
1MByte
TCXO
GPS_VCC
(+3.3 V DC)
2 x PWRCTL
(RFPC)
T-MARK
GPS
_
SDI 1
GPS_SDO 1
GPS_SDO 2
GPS_SDI 2
12 x GPS
_
GPIO
GPS
_
M-RST
BOOTSELECT
GPS_VANT
GPS_VCC_RF
RECEIVER ARCHITECTURE
RTC
Figure 32: Receiver architecture of the GPS receiver
GPS_RFPC0
330
W
Vcc = 3.3 V DC
BC817
47 k
W
GND