Specifications

Position Decoding IP 240
In addition, the following are carried out on the basis of the specified configuring data:
• any outputs that are set are reset
• an interrupt is generated for DRBR or NPUE and interrupt bit DRB or NPU is set in the interrupt
request bytes.
Status bit DRBR is reset on the IP when the fault has been rectified and
• the status area has been read at least once or
• the interrupt request bytes were read ( Section 7.2.7) and the fault that triggered the
interrupt was a wirebreak.
Status bit NPUE is reset on the IP
• following reading of the status area or
• when the interrupt request bytes were read and the fault that triggered the interrupt was a
zero mark monitoring problem.
7.2.7 Interrupt Generation and Processing
Status bits REF 1 to REF 8, UEBL, DRBR and NPUE can trigger an interrupt, and are stored as RF 1 to
RF 8, UEB, DRB and NPU in interrupt request bytes ( Section 7.3.3) on the IP when they show a
”1” value.
Reading the interrupt request bytes
When it detects an interrupt, the CPU invokes an interrupt service OB. In this organization block,
you must invoke a control FB and initialize it for function 3 ”Read interrupt request bytes”. The
control FB transfers the interrupt request bytes for both channels to data words DW 20 and DW 21
in the specified data block. You can react to the cause of the interrupt by evaluating these bytes.
When these bytes are read,
• the bits in the interrupt request bytes on the IP are reset
• the IP revokes the interrupt request
• status bit UEBL or NPUE is reset when one of these errors caused the interrupt and
• status bit DRBR is reset when the error was rectified and a wirebreak signal was the reason for
the interrupt.
Only the DB specified in the relevant control FB parameter can be updated directly, as the
interrupt request bytes are read without regard to a specific channel and the current status can be
read out from the IP on a one-shot basis only.
Note
Status bits UEBL and NPUE, as well as all interrupt bits in the interrupt request
bytes, are reset on the IP 240 once they have been scanned and can therefore be
read out on a one-shot basis only.
Masking interrupts
You can mask all bits with interrupt capability in the relevant channel by setting the AMSK
control bit (D 17.15) and then transferring the control bits to the IP. Masked interrupts do not
generate interrupt requests, and are not stored in the interrupt request byte, i.e. they are lost.
No interrupt is generated when the actual value lies within a track with interrupt capability at the
instant at which interrupt masking is revoked.
7-14 EWA 4NEB 811 6120-02a