Specifications

IP 240 Position Decoding
Traversing speed and track width
In order for entry into a track to be detectable in every module firmware cycle, the traversing
speed must be matched to the minimum track width.
The encoder pulses acquired by the IP are counted in a counter chip. The current (internal) count is
read out once in each module firmware cycle and then postprocessed to produce the (external)
actual value. The track limits are compared to this actual value. To ensure unambiguous detection
track entry, a track must not be entered and then exited in the interval between two count
readouts (t
LZ
). Because the firmware cycle is asynchronous (free-running), t
LZ
is dependent on the
firmware on-load.
The maximum interval between two readouts from the counter chip is computed as follows:
t
LZ max.
= t
ka1 max.
+ t
ka2 max.
+ 2·t
kom max.
where
t
ka1 max.
= maximum processing time for channel 1
t
ka2 max.
= maximum processing time for channel 2
t
kom max.
= maximum processing time for a data interchange
In Chapter 12 ”Response Times” you will find a list of processing times which will help you com-
pute the minimum track width for your application. In the worst case, i.e. maximum times for
channel 1, channel 2 and data interchange, t
LZ max.
computes to 7.5 ms.
7.2.4 Hysteresis
Mechanical disturbances can cause minor changes in the actual value. A fluctuation of the actual
value around a track limit can cause continuous triggering of interrupts and setting and resetting
of outputs. To avoid this, an adjustable hysteresis allows another interrupt to be generated or an
output to be set or reset again only when the actual value has moved away from the track limit by
at least the value defined by the hyteresis. This, in turn, allows the actual value to oscillate in the
range defined by track limit ± hysteresis without triggering an interrupt or affecting an output.
A hyteresis value>0 increases the module firmware's cyle time in dependence on the number of
tracks used ( Chapter 12).
Note
The hysteresis does not affect setting or resetting of the REF bits.
EWA 4NEB 811 6120-02a 7-9