Specifications

Encoder Signals IP 240
Connecting the synchronization signal to the IN input
Fig. 13-6. Timing Diagram for the Synchronization Signal, Positioning Mode
IN signal
Counting
pulses
t
3
t
3
4)3)2)1)
t
1
1) Pulse is not taken into account for new 3) Pulse is taken into account in stored final value.
counting cycle. 4) Pulse is not taken into account in stored final value
2) Pulse is counted in next counting cycle.
These pulses can be counted for the These pulses can be counted for the actual
actual value before or after the value before or after the negative IN edge.
positive IN edge.
t
1
: min. 7.5 ms t
2
: min. 500 µst
3
: min. 7.0 ms
t
2
t
2
13.3 Timing at Counting Input CLK and at Binary Input GT
Signal inputs CLK (clock) and GT (gate) are used in counting mode.
Only bounce-free 24 V encoders may be used. Coding switches S5 and S6 must be set to 24 V. It is
also possible to connect 3-wire and 4-wire BERO proximity switches.
Because the GT signal is also evaluated by the IP 240 module firmware, care must be taken that
the signal be present for at least 5 ms as active signal and 5 ms as inactive signal. The maximum
frequency is 100 Hz.
To enable defined counter operation, times t
1
and t
2
must be carefully observed for the first CLK
signal while GT=1 or GT=0.
The times and edge steepness given below refer to the signals present on the module.
Fig. 13-7. Timing Diagram for the CLK and GT Signals, Counting Mode
GT signal
CLK signal
GT signal
CLK signal
t
3
t
1
t
2
t
1
: min. 2,5 µst
2
: min 2.5 µst
3
: min. 5 ms t
4
: min. 5 µs
t
4
t
4
t
2
t
1
t
3
13-6 EWA 4NEB 811 6120-02a