Specifications

IP 240 Response Times
Fig. 12-3. Response Time for Evaluation of the Actual Value and of Wirebreak
and Zero Mark Errors
Setpoint reached
or error has
occured
t
1
t
1
Status bit is updated
Interrupt is generated
Output is set
Output is reset
Position decoding and positioning
modes
Counting
mode
t
reak
1) 1)
t
reak
t
1
=max. 50 µs (when ohmic load and I
output
=50 mA)
1) Is reset following reading of the interrupt request bytes
Fig. 12-4. Response Time for Evaluation of Inputs IN and GT
t
1
t
1
t
reak
t
reak
t
1
=max. 50 µs (when ohmic load and I
output
=50 mA)
1) Is reset following reading of the interrupt request bytes
t
1
1)
t
reak
t
reak
IN/GT input
Interrupt IRx is generated
Output is switched
Status bit is updated
Counting
mode
Position decoding and positioning
modes
Note
Switching of the IP outputs is
• firmware-controlled in position decoding and positioning mode.
• counter chip controlled in counting mode and thus independent of the module
firmware's response time.
EWA 4NEB 811 6120-02a 12-3