Specifications

Counting IP 240
Control bits
DL 17
DR 17
7
Data
byte
6 5 4 3 2 1 0
0
0
0
STRT
0
0
0
0
DA1F
0
DA1S
0
AMSK
0
0
0
Bit
AMSK =1 All process interrupts for the channel are masked, i.e. lost
=0 Process interrupts enabled
DA1F DA1S
0 0 Digital output D1 is reset
0 1 Digital output D1 is set and reset on a mode-dependent basis
1 1 Digital output D1 is set irrespective of the actual value
STRT =1 Enable a count (effective only
=0 Stop a count when EXT=0)
Status bits
DL 18
DR 18
DL 19
DR 19
7
Data
byte
6 5 4 3 2 1 0
0
AKTV
0
0
0
TRIG
0
0
0
0
0
0
0
0
0
0
0
0
REF2
UEBL
0
0
REF1
SG
Bit
0
0
0
0
DA1
0
0
0
DA1 =1 Digital output D1 is set
=0 Digital output D1 is not set
AKTV =1 Count has been enabled
=0 Count has not been enabled
TRIG =1 Counting has started (first counting pulse acquired)
REF1 =1 Actual value has reached ”0”
=0 Actual value has not yet reached ”0”
REF2 =1 The last count was terminated with a negative GATE edge and the final value stored
UEBL =1 Negative actual value range violation (actual value < - 9, 999)
SG =1 Actual value specified in DW 31 and DW 33 is negative
=0 Actual value specified in DW 31 and DW 33 is positive
8-14 EWA 4NEB 811 6120-02a