Specifications

Counting IP 240
When the defined actual value range is exceeded, the counter enters overrange and the IP sets
status bit UEBL (overflow).
When set, the UEBL bit can trigger an interrupt. You must indicate whether or not it is to do so via
the PRA parameter during configuring ( Section 8.3.1). The UEBL bit is reset when the status
area or interrupt request bytes are read.
When the counter has entered the overrange, the pulses are only counted. The next zero crossing
does not generate another interrupt, and digital output D1 is not set.
Transferring a new initial value ANF to the IP
The first time an initial value is transferred to the IP, it is taken from the DB with configuring
FB 171 and then displayed as an actual value.
You can, at any time, transfer a new initial value to the IP. It takes effect, however, only after
termination of the current counting cycle when a positive-going edge occurs in the gate signal.
To transfer a new initial value, enter the new count value in data word 35 of the DB. Now call
control FB 172 and initialize it for function 4 ”Write initial count”. The CPU then transfers the new
initial value to the IP.
Reading the actual value
The actual value is updated on the IP in every module firmware cycle (the firmware is the IP 240's
operating system).
For you to be able to read the current actual value from the DB, you must first call control FB 172
and initialize function 1 ”Reading the actual value, the final value and the status bits”
( Section 8.3.2).
The CPU then transfers the current data from the IP to the data block. The data for the actual
value are entered as follows:
• DW 31 Absolute actual value, in BCD code
• DW 33 Absolute actual value, in binary code
• D 19.0 Sign of the actual value (status bit SG)
After configuration, the initial value transferred is specified as actual value.
Monitoring actual value ”0”
If the actual value reaches ”0”, status bit REF1 is set.
When set, REF1 can
• trigger an interrupt. You must indicate as much in the PRA parameter.
• set digital output D1. You must specify this option in the DIG parameter ( Section 8.3.1).
At the start of a new counter, a positive gate signal edge resets REF1. If the count begins with
”0”, the first counting pulse sets REF1. Output D1 is not set.
8-2 EWA 4NEB 811 6120-02a