Product manual

IP 266 Communication Between the CPU and the IP 266
7 Communication Between the CPU and the IP 266
The IP 266 can be plugged into slots 0 to 7 of the S5-100U programmable
controller. Eight bytes are reserved in both the process input (PII) and process
output (PIO) image for each slot. The CPU and the IP 266 use all eight bytes of the
PII and the PIO to interchange data. Please note that the IP 266 requires version
6ES5-100-8MA02, or a newer version, of the CPU 100.
In this manual, an interchange of data is referred to as a "frame". From the
STEP 5 point of view, there are two types of "frames":
Data interchange: PLC CPU IP 266 Output frame
Data interchange: IP 266 PLC CPU Input frame
Table 7-1. Module Address Assignments
CPUPS
Analog
addresses
64
to
71
72
to
79
80
to
87
88
to
95
96
to
103
104
to
111
112
to
119
120
to
127
0 1 2 3 4 5 6 7
SLOTS
The slots from
8 up may not
be used
98
The permissible address range is from 64 to 127. The IP 266 is addressed with byte-
oriented or word-oriented Load and Transfer statements, as are analog input or
analog output modules.
Figure 7-1. Example of Data Interchange Between CPU and IP 266 (in slot 3)
LIW88, LIW90, LIW92 and LIW94
TQW88, TQW 90, TQW92 and TQW94
CPU
IP
266
EWA 4NEB 812 6057-02 7-1